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Datasheet> All Categories > semiconductor> Programmable logic devices> XA2C32A-7VQG44Q
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XA2C32A-7VQG44Q

Description
FLASH PLD, 6 ns, PQFP44
Categorysemiconductor    Programmable logic devices   
File Size310KB，14 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
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XA2C32A-7VQG44Q Overview

FLASH PLD, 6 ns, PQFP44

XA2C32A-7VQG44Q Parametric

Parameter NameAttribute value
Number of input and output buses33
Number of terminals44
Minimum operating temperature-40 Cel
Maximum operating temperature125 Cel
Processing package description10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
each_compliYes
EU RoHS regulationsYes
stateActive
Programmable logic typeFLASH PLD
in_system_programmableYES
jesd_30_codeS-PQFP-G44
jesd_609_codee3
jtag_bsYES
moisture_sensitivity_level3
Dedicated input quantity0.0
umber_of_macro_cells32
organize0 DEDICATED INPUTS, 33 I/O
Output functionMACROCELL
Packaging MaterialsPLASTIC/EPOXY
ckage_codeTQFP
ckage_equivalence_codeTQFP44,.47SQ,32
packaging shapeSQUARE
Package SizeFLATPACK, THIN PROFILE
eak_reflow_temperature__cel_260
wer_supplies1.5/3.3,1.8
gation_delay6 ns
qualification_statusCOMMERCIAL
screening_levelAEC-Q100
seated_height_max1.2 mm
sub_categoryProgrammable Logic Devices
Rated supply voltage1.8 V
Minimum supply voltage1.7 V
Maximum supply voltage1.9 V
surface mountYES
CraftsmanshipCMOS
Temperature levelAUTOMOTIVE
terminal coatingMATTE TIN
Terminal formGULL WING
Terminal spacing0.8000 mm
Terminal locationQUAD
ime_peak_reflow_temperature_max__s_30
length10 mm
width10 mm
dditional_featureREAL DIGITAL DESIGN TECHNOLOGY

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0
R
XA2C32A CoolRunner-II
Automotive CPLD
0
0
DS552 (v1.1) May 5, 2007
Product Specification
Features
•
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
Guaranteed to meet full electrical specifications over
T
A
= -40° C to +105° C with T
J
Maximum = +125° C
(Q-grade)
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
Available in Pb-free 44-pin VQFP with 33 user I/O
Advanced system features
- Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
·
Optional DualEDGE triggered registers
- Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state or weak pullup on
selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
·
Superior pinout retention
·
100% product term routability across function
block
- Hot pluggable
Description
The CoolRunner
™
-II Automotive 32-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
The CoolRunner-II Automotive 32-macrocell CPLD is I/O
compatible with standard LVTTL and LVCMOS18,
LVCMOS25, and LVCMOS33 (see
Table 1).
This device is
also 1.5V I/O compatible with the use of Schmitt-trigger
inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II Auto-
motive 32-macrocell device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
•
•
•
•
•
Refer to the CoolRunner™-II Automotive CPLD family data
sheet for architecture description.
WARNING: Programming temperature range of
T
A
= 0° C to +70° C
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS552 (v1.1) May 5, 2007
Product Specification
www.xilinx.com
1

XA2C32A-7VQG44Q Related Products

XA2C32A-7VQG44Q XA2C32A XA2C32A-6VQG44I
Description FLASH PLD, 6 ns, PQFP44 FLASH PLD, 6 ns, PQFP44 FLASH PLD, 6 ns, PQFP44
Number of input and output buses 33 33 33
Number of terminals 44 44 44
Minimum operating temperature -40 Cel -40 Cel -40 Cel
Maximum operating temperature 125 Cel 125 Cel 125 Cel
Processing package description 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
each_compli Yes Yes Yes
EU RoHS regulations Yes Yes Yes
state Active Active Active
Programmable logic type FLASH PLD FLASH PLD FLASH PLD
in_system_programmable YES YES YES
jesd_30_code S-PQFP-G44 S-PQFP-G44 S-PQFP-G44
jesd_609_code e3 e3 e3
jtag_bs YES YES YES
moisture_sensitivity_level 3 3 3
Dedicated input quantity 0.0 0.0 0.0
umber_of_macro_cells 32 32 32
organize 0 DEDICATED INPUTS, 33 I/O 0 DEDICATED INPUTS, 33 I/O 0 DEDICATED INPUTS, 33 I/O
Output function MACROCELL MACROCELL MACROCELL
Packaging Materials PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
ckage_code TQFP TQFP TQFP
ckage_equivalence_code TQFP44,.47SQ,32 TQFP44,.47SQ,32 TQFP44,.47SQ,32
packaging shape SQUARE SQUARE SQUARE
Package Size FLATPACK, THIN PROFILE FLATPACK, THIN PROFILE FLATPACK, THIN PROFILE
eak_reflow_temperature__cel_ 260 260 260
wer_supplies 1.5/3.3,1.8 1.5/3.3,1.8 1.5/3.3,1.8
gation_delay 6 ns 6 ns 6 ns
qualification_status COMMERCIAL COMMERCIAL COMMERCIAL
screening_level AEC-Q100 AEC-Q100 AEC-Q100
seated_height_max 1.2 mm 1.2 mm 1.2 mm
sub_category Programmable Logic Devices Programmable Logic Devices Programmable Logic Devices
Rated supply voltage 1.8 V 1.8 V 1.8 V
Minimum supply voltage 1.7 V 1.7 V 1.7 V
Maximum supply voltage 1.9 V 1.9 V 1.9 V
surface mount YES YES YES
Craftsmanship CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
terminal coating MATTE TIN MATTE TIN MATTE TIN
Terminal form GULL WING GULL WING GULL WING
Terminal spacing 0.8000 mm 0.8000 mm 0.8000 mm
Terminal location QUAD QUAD QUAD
ime_peak_reflow_temperature_max__s_ 30 30 30
length 10 mm 10 mm 10 mm
width 10 mm 10 mm 10 mm
dditional_feature REAL DIGITAL DESIGN TECHNOLOGY REAL DIGITAL DESIGN TECHNOLOGY REAL DIGITAL DESIGN TECHNOLOGY

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