DS1384FP-12 datasheet, PDF - EEWORLD Datasheet

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DS1384FP-12: Description1 TIMER(S), REAL TIME CLOCK, PQFP44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size482KB，18 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1384FP-12 Overview

1 TIMER(S), REAL TIME CLOCK, PQFP44

DS1384FP-12 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	QFP
package instruction	10 X 10 MM, 2 MM HEIGHT, MQFP-44
Contacts	44
Reach Compliance Code	_compli
ECCN code	EAR99
maximum clock frequency	0.032 MHz
External data bus width	8
Information access methods	PARALLEL, DIRECT ADDRESS
interrupt capability	Y
JESD-30 code	S-PQFP-G44
JESD-609 code	e0
length	10 mm
Humidity sensitivity level	3
Number of terminals	44
Number of timers	1
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP44,.57SQ,32
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	2.45 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
shortest time	1/100 SECOND
Maximum time at peak reflow temperature	20
Volatile	YES
width	10 mm
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK

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DS1384

Watchdog Timekeeping Controller

www.maxim-ic.com

FEATURES

Keeps Track of Hundredths of Seconds,

Seconds, Minutes, Hours, Days, Date of the

Month, Months, and Years with Leap Year

Compensation Valid Up to 2100

Watchdog Timer Restarts an Out-of-

Control Processor

Alarm Function Schedules Real-Time

Related Activities

Programmable Interrupts and Square-

Wave Outputs

Bytewide RAM-Like Access

50 Bytes of On-Board User RAM

Greater Than 10 Years Timekeeping and

Data Retention in the Absence of Power

with Small Lithium Coin Cells

Supports Up to 128k x 8 of External Static

RAM

All Timekeeping Registers and On-Board

RAM are Individually Addressable via the

Address and Data Bus

PIN CONFIGURATION

TOP VIEW

GND

A16

INTA

CCO

SQW

PFO

BAT2

INTB/(INTB)

N.C.

A14

A12

DQ0

DQ1

DQ2

GND

DQ3

DQ4

DQ5

DQ6

DQ7

DS1384

CEO

A15

BAT1

A13

A11

A10

MQFP

ORDERING INFORMATION

PART

DS1384FP-12

DS1384FP-12+

TEMP RANGE

0°C to +70°C

VOLTAGE (V)

5.0

PIN-PACKAGE

44 MQFP

TOP MARK*

DS1384FP

Denotes lead-free/RoHS-compliant device.

A “+” anywhere on the top mark indicates a lead-free/RoHS-compliant device.

1 of 17

REV: 112105

DS1384

contention. However, if the output bus has been enabled (CE and

active), then

will disable the

outputs in t

WEZ

from its falling edge.

When the address value presented to the DS1384 during the write is in the range of 00000H through

0003FH, one of the 64 on-chip registers will be selected and data will be written into the device.

When the address value presented to the DS1384 during the write is in the range of 00040H through

1FFFFH, an external SRAM location will be selected.

DATA RETENTION MODE

When V

CCI

is within nominal limits (V

> 4.5V) the DS1384 can be accessed as described above with

read or write cycles. However, when V

is below the power-fail point, V

, (point at which write

protection occurs) the internal clock registers and external RAM is blocked from access. This is

accomplished internally by inhibiting access to the clock registers via the

signal. At this time the

power fail output signal (PFO) is driven active and will remain active until V

returns to nominal levels.

External RAM access is inhibited in a similar manner by forcing

CEO

to high level. This level is within

0.2 volts of the V

CCI

input.

CEO

will remain at this level as long as V

CCI

remains at an out-of-tolerance

condition. When V

CCI

falls below the level of the battery (V

BAT1

or V

BAT2

), power input is switched from

the V

CCI

pin to the V

BAT

pin and the clock registers are maintained from the attached battery supply.

External RAM is also powered by the V

BAT

input when V

CCI

is below V

BAT

pin through the V

CCO

pin. The

CCO

pin is capable of supplying 100µA of current to the attached memory with less than 0.3V drop

under this condition. On power-up, when V

CCI

returns to in-tolerance conditions, write protection

continues for 150ms by inhibiting

CEO.

The

PFO

signal also remains active during this time. The

DS1384 is capable of supporting two batteries which are used in a redundant fashion for applications

which require added reliability or increased battery capacity. When two batteries are used, the higher of

the two is selected for use. A selected battery will remain as backup supply until it is significantly below

the other. When the selected battery voltage falls below the alternate battery by about 0.6V, the alternate

battery is selected and then becomes the backup supply. This switching occurs transparently to the user

and continues until both batteries are exhausted. When only a single battery is required, both battery

inputs can be connected together. However, a more effective method of using a single battery supply is to

ground the unused battery input. When using a single battery, V

BAT1

is the preferred input.

WATCHDOG TIMEKEEPER REGISTERS

The DS1384 Watchdog Timekeeper Controller has 14 internal registers, which are 8 bits wide and

contain all of the Timekeeping, Alarm, Watchdog, Control, and Data information. The Clock, Calendar,

Alarm and Watchdog Registers are memory locations, which contain external (user accessible) and

internal copies of the data. The external copies are independent of internal functions except that they are

updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The

Command Register bits are affected by both internal and external functions. This register will be

discussed later. The 50 bytes of RAM registers are accessed from the external address and data bus and

reside or overlay external static RAM. Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day and date

information (see Figure 2). Time of day information is stored in BCD. Registers 3, 5, and 7 contain the

time of day alarm information. Time of day alarm information is stored in BCD. Register B is the

Command Register and information in this register is binary. Register C and D are the Watchdog Alarm

Registers and information, which is stored in these two registers, is in BCD. Registers 0000EH through

5 of 18

DS1384FP-12 Related Products

	DS1384FP-12	DS1384	DS1384FP
Description	1 TIMER(S), REAL TIME CLOCK, PQFP44	1 TIMER(S), REAL TIME CLOCK, PQFP44	1 TIMER(S), REAL TIME CLOCK, PQFP44
Maker	Maxim	Maxim	-
package instruction	10 X 10 MM, 2 MM HEIGHT, MQFP-44	QFP,	-
Reach Compliance Code	_compli	unknow	-
ECCN code	EAR99	EAR99	-
External data bus width	8	8	-
Information access methods	PARALLEL, DIRECT ADDRESS	PARALLEL, DIRECT ADDRESS	-
JESD-30 code	S-PQFP-G44	S-PQFP-G44	-
JESD-609 code	e0	e0	-
Number of terminals	44	44	-
Number of timers	1	1	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	QFP	QFP	-
Package shape	SQUARE	SQUARE	-
Package form	FLATPACK	FLATPACK	-
Certification status	Not Qualified	Not Qualified	-
Nominal supply voltage	5 V	5 V	-
surface mount	YES	YES	-
technology	CMOS	CMOS	-
Terminal surface	Tin/Lead (Sn/Pb)	TIN LEAD	-
Terminal form	GULL WING	GULL WING	-
Terminal location	QUAD	QUAD	-
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK	TIMER, REAL TIME CLOCK	-

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