OC-3/STS3/STM-1 rates, concatenated and non-concat-
enated
• Complies with ITU-Standards G.707/Y.1322 and
G.783
[1,2]
• Complies with Bellcore GR253 rev.1, 1997
[3]
• Channelized operation: supports 16xOC-3 and 4xOC-12
within OC-48 stream
• Supports TUG3 mapping in SDH mode
• Virtual concatenation enables secure and dedicated
bandwidth provisioning
[4]
• Up to 16 channels
• From 50-Mbps to 1.2-Gbps bandwidth per channel
• STS-1 and STS-3c granularity
• Full duplex mapping of ATM cells over SONET/SDH
• Complies with ITU-Standards I 432.2
[5,6,7]
• Full duplex mapping of packet-over-SONET/SDH: IETF
RFC 1619/1662/2615 (HDLC/PPP)
[8,9,10]
• Generic Framing Procedure (GFP) per ANSI
T1X1.5
[11,12,13]
Protocol Encapsulator/Decapsulator
delineates GFP frames with length-CRC frame
construct
• GFP 268r1
• User-programmable encapsulation
• User-programmable clear channel transport
• User-programmable SONET/SDH bypass
• Programmable frame tagging engine for packet
preclassification enables such features as
• MPLS label lookup and tagging
• PPP: LCP and NCP tagging
• PPP control packets optionally sent to host CPU
interface
• MAC/layer 3 address look up and tagging.
• Programmable A1A2 processing bypass in Rx direction
with frame sync input
• Complete section overhead (SOH), line overhead
(LOH), and path overhead (POH) processing
• APS extraction, CPU interrupt generation, and
programmable insertion of APS byte
• Line side APS port interface
• Provision for protection switching on SONET/SDH port
• Programmable PRBS generator and receiver
• Serial port to access line/section data communication
channel (DCC) and voice communication channel
(VCC)
• Full duplex OIF-SPI (POS-PHY)/UTOPIA level 3
interface
[14,15]
• 16-bit/32-bit host CPU interface bus
• JTAG and boundary scan
• Glueless interface with Cypress CYS25G0101DX
OC-48 PHY
• 0.18-um CMOS, 504-pin BGA package
• +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for
HSTL/LVPECL I/O supply, and +0.75V/2.0V reference
Applications
• Multi-service nodes
• ATM switches and routers
• Packet routers and multiservice routers
• SONET/SDH/Add-Drop Mux for packet/data applications
• SONET/SDH/ATM/POS test equipment
Notes:
1. ITU-T Recommendation G.707. “Network Node Interface for the Synchronous Digital Hierarchy.” 1996.
2. ITU-T Recommendation G.783. “Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks.” 2000.
3. Bellcore Publication GR-253-Core. “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.” 1997.
4. Jones, N., Lucent Microelectronics, and C. Murton, Nortel Networks. “Extending PPP over SONET/DSH with Virtual Concatenation, High-Order and Low-Order
6. American National Standards Institute. “Synchronous Optical Network (SONET)—Basic Description Including Multiplex Structure, Rates and Formats.” ANSI
T1.105-1995.
7. American National Standards Institute. “Synchronous Optical Network (SONET)—Payload Mappings.” ANSI T1.105.02–1998.
8. Simpson, W. “PPP over SONET/SDH.” RFC 1619. May 1994.
9. Simpson, W., ed. “PPP in HDLC-like Framing,” RFC 1662.
Daydreamer.
July 1994.
10. Malis, A. and W. Simpson. “PPP over SONET/SDH,” RFC 2615. June 1999.
11. Hernandez-Valencia, E., Lucent Technologies. “A Generic Frame Format for Data over SONET (DoS).” March 2000.
12. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999.
13. Hernandez-Valencia, E., Lucent Technologies. T1X1.5/2000-209. “Generic Framing Procedure (GFP) Specification.” October 9–13, 2000.
15. Can, R. and R. Tuck. “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link-Layer Devices.” OIF-SPI3-01.0. June 2000.
Cypress Semiconductor Corporation
Document #: 38-02078 Rev. *G
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 25, 2005
CONFIDENTIAL
NoBL
SRAM
CY7C9536B
E /O
LAN, CBR,
c lie n t
p o r ts , e tc .
L in k L a y e r
D e v ic e fo r
E th e r n e t,
FC, DVB,
A T M , e tc .
SPI - 3
HBST
U T O P IA
P O S IC
D e v ic e
CYS25G 0101DX
O C -4 8
T r a n s c e iv e r
O /E
CPU
Figure 1. POSIC2GVC System Application Diagram
POSIC2GVC Logic Block Diagram
TXD[31:0]
TXCLKI
TXCLKOUT
TXFRAME_PULSE
SONETTX_PAROUT
TX SONET Line Interface
POHSDIN
TOHSDIN
TE1STROBE
TE2STROBE
SONET
Transmit SONET Framing
Overhead Processor Bypass
Pointer Processor
Transmit SONET
Text
Framer
RXD[31:0]
RXCLK
RXFRAME_PULSE
RXCLKs
SONETRX_PARIN
LFI
RX SONET Line Interface
Receive SONET
Receiv
e De-Framer
SONET
SONE
Receive SONET
Framing T
Overhead
Overhe
Processor
Bypass ad
Pointer
Insertio Processor
n
Clk16MHz
Clk2MHz
POHSDOUT
RPOHSTART
TPOHSTART
RE1STROBE
RE2STROBE
TOHSDOUR
VC TX
(Virtual Concatenation)
VC RX
(Virtual Concatenation)
TX
ATM
Encapsulator
TX
HDLC
Encapsulator
TX
Generic
Framing
Procedure
(GFP)
Encapsulator
RX
RX
ATM
HDLC
Decapsulator Decapsulator
RX
Generic
Framing
Procedure
(GFP)
Decapsulator
TCK
TRST
TDI
TMS
TDO
General
Pins
JTAG
Interface
Programmable
Frame Tagging
Transmit UTOPIA/SPI-3
Interface
CPU
Interface
Receive UTOPIA/SPI-3
Interface
RST_n
SYSCLK
RSTOUT_n
CLKOUT
TEST[2:0]
POSIC_OEN
SCAN_ENA
TFCLK
TERR
TDAT[31:0]
TPRTY
TADD[3:0]
TMOD[1:0]
TSOP
TEOP
STPA
PTCA
TENB
TSX
DTCA[3:0]
CpuClk
CpuTs_n/
CapuAds_n
CpuSel
CpuBlast_n
CpuTa_n
ChipSel
CpuInt
CpuClkFail
CpuWrRd
CpuAD[31:0]
Mode
RVAL
RENB
RFCLK
RDAT[31:0]
RADD[7:0]
RMOD[1:0]
RPRTY
RERR
REOR
RSOP
RCA
RSX
Document #: 38-02078 Rev. *G
Page 2 of 46
CONFIDENTIAL
Overview
The CY7C9536B (POSIC2GVC) is a highly integrated
SONET/SDH framer device for transport of ATM and IP
packets over SONET/SDH links. It features special functions
and architecture to support next-generation optical networking
protocols for both SONET/SDH and direct data-over-fiber
networks. OIF-SPI (POS-PHY) level 3, UTOPIA level 3 and
High-Bandwidth Synchronous Transfer (HBST) interfaces are
provided on the system side.
POSIC2GVC performs complete SOH, LOH, and POH
processing. Complete access to all overhead bytes is provided
through register access via the host CPU interface. Access to
selected overhead bytes are also available through serial port.
Optional frame sync input and Transport Overhead (TOH)
bypass enables better interface with STS-1 switched streams.
The virtual concatenation feature, with up to 16 channels,
enables provisioning of secure, dedicated and right-sized
bandwidth for Ethernet or ATM transport. Up to 16 virtual
channels can be created with STS-1 or STS-3c granularity.
Bandwidth from 50 Mbps to 1.2 Gbps can be allocated per
channel.
POSIC2GVC supports packet over SONET/SDH as PPP in
HDLC-like frame as per IETF rfc 1619/1662/2615 (PPP).
POSIC2GVC also supports full duplex ATM over SONET/SDH
transport in compliance with ITU I432.2.
POSIC2GVC supports the new generation Generic Framing
Procedure (GFP) protocol encapsulation/Decapsulation over
SONET/SDH. This protocol engine features wire rate framing,
frame delineation and deframing with length-CRC pair header
construct. Optional payload scrambling/descrambling and
payload FCS are also provided.
Clear channel mode enables transport of any raw byte
streams on selected virtual channels, while the rest of the
channels are transporting data through any one of encapsu-
lation/decapsulation engines.
The Programmable Frame Tagging Engine enables wire rate
tagging of packets/frames. For new generation networking
features such as MPLS, this engine can be programmed to tag
based on existence/lack of specific label/field values, in the
first 64 bytes of each packet. This way, packets are tagged for
a variety of conditions, all programmable by the user, enabling
sorting of packets in the incoming data stream and buffering
packets accordingly. In a PPP application, control packets can
optionally be sent over the host CPU interface directly.
SONET/SDH bypass mode allows use of this device for data
transport in non SONET/SDH point-to-point and mesh optical
networks.
CY7C9536B
or HBST operations. In these cases, the first data transfer
always carry the channel number.
POSIC2GVC supports three basic types of encapsulation,
namely (i) ATM, (ii) HDLC frame, and (iii) GFP (frames with
length-CRC pair header construct based delineation). Clear
channel or transparent mode (no encapsulation) is also
supported. While in operation, only one type of encapsulation
can be enabled for all VC channels. Some or all of the VC
channels can be programmed as clear channels. For Clear
Channels, the encapsulator engine will bypass the encapsu-
lation and pass the packets without any processing to the next
block.
Encapsulated packets are transferred to the Virtual Concate-
nation (VC) block along with the channel number. The VC
block rearranges the packet/frame flow to support the
bandwidth allocation for virtual channels. Bandwidth is
assigned by allocating a programmed number of SPEs to each
channel. The VC block keeps track of the SPE under
construction by the SONET/SDH framer block and transfers
the packets meant for a given channel to the SONET framer.
Since POSIC2GVC does not have a packet storage memory
on-chip, a channel bandwidth balanced packet flow is
expected from the system side. To enable such a balanced
transfer, POSIC2GVC has internal FIFO of 512 bytes per
channel. The status of FIFO is provided through pins to the link
layer.
Finally, the SONET/SDH framer inserts the packet /cells into
the SONET/SDH frame. All overhead bytes are added. All
alarm bits and status bits are inserted based on the status of
incoming frames as well as programming done by the host
CPU. The scrambler meets relevant standards and can
optionally be disabled. Frames are finally sent out on the fiber
side interface. If programmed to do so, the SONET/SDH
framer can be bypassed and encapsulated packets/frames
can be sent directly to the fiber-side interface.
Receive
In the receive direction, SONET/SDH frames are received
from the fiber side. Data packets/frames are extracted from the
payload and passed onto the selected decapsulator engine
after compensation for differential delay, in case of virtual
concatenation. If the SONET/SDH framer is bypassed, the
incoming data stream is directly passed over to the decapsu-
lator engine. Data packets/frames are then decapsulated and
sent to the Programmable Frame Tagging Engine. They are
then analyzed and tagged before sent out to the system side
via the OIF-SPI level 3, UTOPIA or HBST interface. Tagging
of frames is optional.
SONET/SDH frames entering from the fiber side are synchro-
nized and the frame boundary is identified with A1A2 bytes.
Frames
can
be
optionally
synchronized
with
Frame_Sync_Input to identify the boundary. Descrambling is
performed to retrieve scrambled frames. Complete processing
of all overhead bytes, Section, Line and Path, is performed
and all alarm bits are verified and alarms are raised as
programmed. Full access to all overhead bytes is provided
through register access. Access to selected overhead bytes is
also provided through serial bus. The SONET/SDH deframing
can be entirely bypassed.
The extracted payload is transferred to the VC block where it
is reorganized to compensate for any differential delay
encountered in the network from the virtual concatenation
Page 3 of 46
Transmit
In the transmit direction, packets are received from the system
side, encapsulated/framed and mapped into the SONET/SDH
payload. Finally the TOH is added and SONET/SDH frames
are passed onto the fiber side/line side interface on a parallel
bus.
The system side interface can be programmed either as
OIF-SPI level 3, or UTOPIA level 3 or HBST modes. In the
UTOPIA mode, ATM cells can be received either in 54- (8-bit
interface) or 56- (8-bit and 32-bit interfaces) bytes format. The
sixth byte carries the channel number of the cell. In case of
packets, the interface can be programmed as OIF-SPI level 3
Document #: 38-02078 Rev. *G
CONFIDENTIAL
channel. For this purpose, up to 256 frames are stored in
external memory. The VC block then passes the payload
stream to the selected decapsulator engine.
The selected decapsulator engine delineates the payload
stream, decapsulates and extracts packets/cells from the
stream. Descrambling of packets/cells is optional. The
packets/cells are then sent out to the programmable Frame
Tagging Engine.
The Frame Tagging Engine optionally tags the packet/cell as
programmed. The packet/cell is then transferred to the link
layer device, through the System Interface (OIF-SPI/UTOPIA
level 3, or HBST), with an additional eight bits of information.
Four bits specify the VC channel and the other four bits specify
the tag.
VC-3-1v/STS-1-1v
[17]
VC-3-2v/STS-1-2v
VC-3-3v/STS-1-3v
VC-3-4v/STS-1-4v
VC-3-5v/STS-1-5v
VC-3-6v/STS-1-6v
VC-3-7v/STS-1-7v
VC-3-8v/STS-1-8v
VC-4-1v/STS-3c-1v
[17]
VC-4-2v/STS-3c-2v
VC-4-3v/STS-3c-3v
VC-4-4v/STS-3c-4v
VC-4-5v/STS-3c-5v
VC-4-6v/STS-3c-6v
VC-4-7v/STS-3c-7v
VC-4-8v/STS-3c-8v
VC-4-4c-1v/STS-12c-1v
[17]
VC-4-4c-2v/STS-12c-2v
VC4-8c-1v/STS-24c-1v
[17]
CY7C9536B
(~50 Mbps)
(~100 Mbps)
(~150 Mbps)
(~200 Mbps)
(~250 Mbps)
(~300 Mbps)
(~350 Mbps)
(~400 Mbps)
(~150 Mbps)
(~300 Mbps)
(~450 Mbps)
(~600 Mbps)
(~750 Mbps)
(~900 Mbps)
(~1.05 Gbps)
(~1.2 Gbps)
(~600 Mbps)
(~1.2 Gbps)
(~1.2Gbps)
Table 1. Virtual Concatenated Channel Bandwidth
[16]
Virtual Concatenation
Virtual concatenation creates multiple virtual payloads of
different sizes within the incoming SONET/SDH frame, effec-
tively creating multiple channels of different bandwidth.
The advantages of VC are:
• Efficient and dedicated bandwidth allocation.
• Compatibility with TDM access infrastructure. Virtually
concatenated channels can coexist with aware and
nonaware Network Elements on the same shared access.
• Independence from upper layer data protocol/frame format.
• Fine granularity channels are extensible and easily provi-
sionable.
POSIC2GVC supports VC for all types of packets/frames/
protocols it transports on SONET/SDH. Up to 16 channels can
be created using STS1/VC-3, STS3c/VC-4, STS12c/VC4-4c
and STS24c/VC4-8c. POSIC2GVC also supports non-virtually
concatenated channels such as STS3c and STS12c.
Table 1
shows a list of virtually concatenated channel bandwidth
supported by POSIC2GVC.
Virtual concatenation requires specific overhead processing
capabilities only at the path terminating equipment. It remains
transparent at the intermediate nodes in the network. It is
possible therefore that two or more different SPEs, virtually
bonded to create a channel, travel through different routes in
the network. Hence, they can arrive at the destination in the
order different from the order at the point of origination. Delay
encountered in arrival of two virtually concatenated SPEs in a
frame is called differential delay. To compensate for differential
delay, the SPE received earlier need to be stored until the
particular SPE, which is previous in the order but faces longer
travel time, arrives at the terminating node. POSIC2GVC can
store up to 256 SONET/SDH frames in external memory,
which can compensate for ±16 ms of differential delay. For
differential delay higher than that, POSIC2GVC raises an
alarm.
Notes:
16. All VC mode channel configurations require a SYSCLK frequency of 133.33 MHz.
17. Please refer to device manual for allowed combinations of Virtual Channels using STSX-1v/VCX-1v granularity.
Document #: 38-02078 Rev. *G
Page 4 of 46
CONFIDENTIAL
(Gigabit
1Gb Ethernet)
Packet
SPI - 3
SPI - 3
1Gb
Packet
CH
2 (Gigabit
Ethernet)
P
O
S
I
C
SONET
Cloud
P
O
S
I
C
CY7C9536B
CH
1
1Gb
CH
Packet
1
Link
Layer
Link
Layer
1Gb
Packet CH
(Gigabit 2
Ethernet)
300Mb
(3x100 Mb
Ethernet
OR TDM in
clear channel
mode)
CH
3
300Mb
CH
3
(3x100 Mb
Ethernet
OR TDM in
clear channel
mode)
15
CH
1
3
SONET
Cloud
1
2
n
16
16
CH
1
3
2
1
CH
2
(OC3 SPEs may arrive in different order.
At receiveing end, POSIC stores the SPEs in
external memory to re-arrange them in correct order.)
15
n
CH
3
CH
3
CH
2
Figure 2. Explanation of Virtual Concatenation
Generic Frame Encapsulation/Decapsulation
POSIC2GVC supports a variety of protocols/packets/frames
to transport over a SONET/SDH link. For clarity of reference,
in this document, framing of packets/cells into these protocols
is called “encapsulation,” and the engine performing encapsu-
lation is called an “encapsulator.” Similarly, deframing is called
“decapsulation,” and the engine performing decapsulation is
called a “decapsulator.”
Three different encapsulator and decapsulator engines are
integrated into POSIC2GVC.
The ATM encapsulator computes and adds the HEC field,
scrambles the cells and passes on to the VC block. In case of
underflow, ATM encapsulator also creates programmable idle
cells.
The ATM decapsulator checks for HEC and integrity of the cell.
It descrambles the cells, isolates and discards idle cells and
passes ATM cells to the Programmable Frame Tagging
Engine.
HDLC encapsulator performs Asynchronous Control
Character Mapping (ACCM), stuffing, flag sequence insertion
and scrambling. Optionally, up to 16 bytes of header is inserted
ahead of the packet while framing the packet. The host CPU
can program this 16-byte header through register programing.
Such programmable header insertion enables encapsulation
of PPP, frame relay or other protocol.
The HDLC decapsulator descrambles the incoming byte
stream and searches the flag sequence. Upon finding the
boundary, decapsulator performs destuffing and ACCM
demapping before passing the packets to the Programmable
Frame Tagging Engine.
The Generic Framing Procedure (GFP) Encapsulator/Decap-
sulator supports delineation based on length-CRC pair header
construct. In the transmit direction, it computes a 16-bit header
CRC based on 2-byte length value received from the link layer
device. The length and CRC fields are inserted as header of
the frame ahead of the packet. Scrambling of the payload and
32-bit payload CRC computation and insertion are optional.
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