This input must be at the same voltage rail as input reference clock.
See
Table 2
on page 4.
Output enable/disable input.
See
Table 3
on page 4.
Clock stop enable/disable input.
See
Table 3
on page 4.
PLL enable/disable input.
See
Table 3
on page 4.
Reference select input.
See
Table 3
on page 4.
VCO divider select input.
See
Tables 3, 4 and 5.
Frequency select input, Bank (A:C).
See
Table 4
on page 4.
Feedback dividers select inputs.
See
Table 5
on page 5.
2.5V or 3.3V Power supply for bank A output clocks
[2,3]
2.5V or 3.3V Power supply for bank B output clocks
[2,3]
QC0
VSS
CY29775
QC2
VSS
QB0
2
3
6
8
11, 52
7, 4, 5
20, 14
17, 22, 26
33, 37, 41
MR#/OE
CLK_STP#
PLL_EN
TCLK_SEL
VCO_SEL(1,0)
SEL(A:C)
FB_SEL(1,0)
VDDQA
VDDQB
I, PU
I, PU
I, PU
I, PD
I, PD
I, PD
I, PD
Supply
Supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
VDD
Notes
1. PU = Internal pull up, PD = Internal pull down
2. A 0.1-μF bypass capacitor must be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high
frequency filtering characteristics is cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
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