Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33984
Rev 4.0, 09/2004
Advance Information
Dual Intelligent High-Current
Self-Protected Silicon High-Side
Switch (4.0 mΩ)
The 33984 is a dual self-protected 4.0 mΩ silicon switch used to replace
electromechanical relays, fuses, and discrete devices in power management
applications. The 33984 is designed for harsh environments, and it includes
self-recovery features. The device is suitable for loads with high inrush current,
as well as motors and all types of resistive and inductive loads.
33984
DUAL HIGH-SIDE SWITCH
4.0 mΩ
Freescale Semiconductor, Inc...
Programming, control, and diagnostics are implemented via the Serial
Peripheral Interface (SPI). A dedicated parallel input is available for alternate
and pulse-width modulation (PWM) control of each output. SPI-programmable
fault trip thresholds allow the device to be adjusted for optimal performance in
the application.
The 33984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN
package with exposed tabs.
Features
• Dual 4.0 mΩ Max High-Side Switch with Parallel Input or SPI Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0
µA
• Output Current Monitoring with Two SPI-Selectable Current Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Pin Status, and Program Status
• Enhanced -16 V Reverse Polarity V
PWR
Protection
Bottom View
PNA SUFFIX
SCALE 1:1
CASE 1402-02
16-TERMINAL PQFN (12 x 12)
ORDERING INFORMATION
Device
MC33984PNA/R2
Temperature
Range (T
A
)
-40
°
C to 125
°
C
Package
16 PQFN
Simplified Application Diagram
33984 Simplified Application Diagram
V
DD
V
DD
V
DD
33984
V
DD
V
PWR
V
PWR
GND
I/O
I/O
SO
SCLK
CS
MCU
SI
I/O
I/O
I/O
A/D
FS
WAKE
SI
HS1
SCLK
CS
SO
HS0
RST
IN0
IN1
CSNS
FSI GND
LOAD
LOAD
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
PWR GND
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V
DD
V
IC
V
PWR
I
UP
Internal
Regulator
Overvoltage
Protection
CS
SO
SPI
3.0 MHz
Programmable
Switch Delay
0 ms –525 ms
Selectable Slew
Rate Gate Drive
Freescale Semiconductor, Inc...
SI
SCLK
FS
IN[0:1]
RST
WAKE
Selectable Overcurrent
High Detection
100 A or 75 A
Selectable Over-
current Low Detection
Blanking Time
0.15 ms–155 ms
Selectable Overcurrent
Low Detection
7.5 A –25 A
Open Load
Detection
I
DWN
R
DWN
Overtemperature
Detection
HS0
Logic
HS0
HS1
Programmable
Watchdog
310 ms–2500 ms
V
IC
I
UP
Selectable
Output Current
Recopy
1/20500 or 1/41000
HS1
FSI
GND
Figure 1. 33984 Simplified Internal Block Diagram
CSNS
33984
2
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
Transparent Top View of Package
CSNS
WAKE
RST
IN0
FS
FSI
CS
SCLK
SI
V
DD
SO
IN1
1
2
3
4
5
13
6
GND
7
8
9
10
11
12
16
14
V
PWR
HS0
15
HS1
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TERMINAL DEFINITIONS
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 15.
Terminal
1
Terminal
Name
CSNS
Formal Name
Output Current Monitoring
Definition
This terminal is used to output a current proportional to the designated HS0-1 output.
That current is fed into a ground-referenced resistor and its voltage is monitored by an
MCU's A/D. The channel to be monitored is selected via the SPI. This terminal can be
tri-stated through SPI.
This terminal is used to input a logic [1] signal so as to enable the watchdog timer
function. An internal clamp protects this terminal from high damaging voltages when the
output is current limited with an external resistor. This input has a passive internal
pulldown.
This input terminal is used to initialize the device configuration and fault registers, as
well as place the device in a low current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic LOW to logic HIGH. This terminal should
not be allowed to be logic HIGH until V
DD
is in regulation. This terminal has a passive
internal pulldown.
This input terminal is used to directly control the output HS0. This input has an active
internal pulldown current source and requires CMOS logic levels. This input may be
configured via SPI.
This is an open drain configured output requiring an external pullup resistor to V
DD
for
fault reporting. When a device fault condition is detected, this terminal is active LOW.
Specific device diagnostic faults are reported via the SPI SO terminal.
The value of the resistance connected between this terminal and ground determines
the state of the outputs after a watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF, ON, or the output HSO only is ON. When the FSI
terminal is connected to GND, the watchdog circuit and fail-safe operation are disabled.
This terminal incorporates an active internal pullup current source.
This input terminal is connected to a chip select output of a master microcontroller
(MCU). The MCU determines which device is addressed (selected) to receive data by
pulling the
CS
terminal of the selected device logic LOW, enabling SPI communication
with the device. Other
unselected
devices on the serial link having their
CS
terminals
pulled-up logic HIGH disregard the SPI communication data sent. This terminal
incorporates an active internal pullup current source.
This input terminal is connected to the MCU providing the required bit shift clock for SPI
communication. It transitions one time per bit transferred at an operating frequency,
f
SPI
, defined by the communication interface. The 50 percent duty cycle CMOS-level
serial clock signal is idle between command transfers. The signal is used to shift data
into and out of the device. This input has an active internal pulldown current source.
2
WAKE
Wake
3
RST
Reset (Active Low)
4
IN0
Serial Input
5
FS
Fault Status (Active Low)
6
FSI
Fail-Safe Input
7
CS
Chip Select (Active Low)
8
SCLK
Serial Clock
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33984
3
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TERMINAL DEFINITIONS (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 15.
Terminal
9
Terminal
Name
SI
Formal Name
Serial Input
Definition
This is a command data input terminal connected to the SPI Serial Data Output of the
MCU or to the SO terminal of the previous device of a daisy chain of devices. The input
requires CMOS logic-level signals and incorporates an active internal pulldown current
source. Device control is facilitated by the input's receiving the MSB first of a serial 8-
bit control command. The MCU ensures data is available upon the falling edge of
SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit
command into the internal command shift register.
This is an external voltage input terminal used to supply power to the SPI circuit. In the
event V
DD
is lost, an internal supply provides power to a portion of the logic, ensuring
limited functionality of the device.
This output terminal is connected to the SPI Serial Data Input terminal of the MCU or
to the SI terminal of the next device of a daisy chain of devices. This output will remain
tri-stated (high impedance OFF condition) so long as the
CS
terminal of the device is
logic HIGH. SO is only active when the
CS
terminal of the device is asserted logic LOW.
The generated SO output signals are CMOS logic levels. SO output data is available
on the falling edge of SCLK and transitions immediately on the rising edge of SCLK.
This input terminal is used to directly control the output HS1. This input has an active
internal pulldown current source and requires CMOS logic levels. This input may be
configured via SPI.
This terminal is the ground for the logic and analog circuitry of the device.
This terminal connects to the positive power supply and is the source input of
operational power for the device. The V
PWR
terminal is a backside surface mount tab
of the package.
Protected 4.0 mΩ high-side power output to the load.
Protected 4.0 mΩ high-side power output to the load.
10
V
DD
Digital Drain Voltage
(Power)
Freescale Semiconductor, Inc...
11
SO
Serial Output
12
IN1
Serial Input
13
14
GND
V
PWR
Ground
Positive Power Supply
15
16
HS1
HS0
High-Side Output 1
High-Side Output 0
33984
4
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Operating Voltage Range
Steady-State
V
DD
Supply Voltage
Input/Output Voltage
(Note 1)
V
DD
V
IN[0:1]
,
RST
, FSI
CSNS, SI, SCLK,
CS, FS
V
PWR
-16 to 41
0 to 5.5
-0.3 to 7.0
V
V
V
SO Output Voltage
(Note 1)
V
SO
I
CL(WAKE)
I
CL(CSNS)
I
HS[0:1]
E
CL[0:1]
V
ESD1
V
ESD2
-0.3 to V
DD
+0.3
2.5
10
30
0.75
V
mA
mA
A
J
V
Freescale Semiconductor, Inc...
WAKE Input Clamp Current
CSNS Input Clamp Current
Output Current
(Note 2)
Output Clamp Energy
(Note 3)
ESD Voltage
Human Body Model
(Note 4)
Machine Model
(Note 5)
±2000
±200
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Storage Temperature
Thermal Resistance
(Note 6)
Junction to Case
Junction to Ambient
Peak Terminal Reflow Temperature During Solder Mounting
(Note 7)
R
θ
JC
R
θ
JA
T
SOLDER
<1.0
20
230
T
A
T
J
T
STG
-40 to 125
-40 to 150
-55 to 150
°
C
°
C
°
C/W
°
C
Notes
1. Exceeding voltage limits on
RST
, IN[0:1], or FSI terminals may cause a malfunction or permanent damage to the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, R
L
= 0, V
PWR
= 12 V, T
J
= 150°C).
4.
5.
6.
7.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω).
ESD2 testing is performed in accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω).
Device mounted on a 2s2p test board according to JEDEC JESD51-2.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33984
5
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