N25Q128A23B1240E datasheet, PDF

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N25Q128A23B1240E: DescriptionFlash, 16MX8, PBGA24, 6 X 8 MM, ROHS COMPLIANT, TBGA-24; Categorystorage storage; File Size6MB，183 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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N25Q128A23B1240E Overview

Flash, 16MX8, PBGA24, 6 X 8 MM, ROHS COMPLIANT, TBGA-24

N25Q128A23B1240E Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	6 X 8 MM, ROHS COMPLIANT, TBGA-24
Contacts	24
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
startup block	BOTTOM
Maximum clock frequency (fCLK)	108 MHz
Data retention time - minimum	20
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PBGA-B24
JESD-609 code	e1
length	8 mm
memory density	134217728 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	24
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA24,5X5,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Serial bus type	SPI
Maximum standby current	0.0001 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
type	NOR TYPE
width	6 mm
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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N25Q128

128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors,

XiP enabled, serial flash memory with 108 MHz SPI bus interface

Features

SPI-compatible serial bus interface

108 MHz (maximum) clock frequency

2.7 V to 3.6 V single supply voltage

Supports legacy SPI protocol and new Quad

I/O or Dual I/O SPI protocol

Quad/Dual I/O instructions resulting in an

equivalent clock frequency up to 432 MHz:

XIP mode for all three protocols

– Configurable via volatile or non-volatile

registers:

Program/Erase suspend instructions

Continuous read (entire memory) via single

instruction:

– Fast Read

– Quad or Dual Output Fast Read

– Quad or Dual I/O Fast Read

Flexible to fit application:

– Configurable number of dummy cycles

– Output buffer configurable

– Fast POR instruction: decrease power-on

time

– Reset function (upon customer request)

64-byte user-lockable, one-time programmable

(OTP) area

Erase capability

– Subsector (4-Kbyte) granularity in the 8

boot sectors (bottom or top parts)

– Sector (64-Kbyte) granularity

Write protections

– Software write protection applicable to

every 64-Kbyte sector (volatile lock bit)

– Hardware write protection: protected area

size defined by non-volatile bits (BP0, BP1,

BP2, BP3 and TB bit)

– Additional smart protections available upon

customer request

Electronic signature

– JEDEC standard two-byte signature

(BA18h)

– Additional 2 Extended Device ID (EDID)

bytes to identify device factory options

– Unique ID code (UID) with 14 bytes read-

only, available upon customer request

More than 100,000 program/erase cycles per

sector

More than 20 years data retention

Packages (all packages RoHS compliant)

– F8 = VDFPN8 8 x 6 mm (MLP8)

– 12 = TBGA24 6 x 8 mm

– F6 = VDFPN8 6 x 5 mm (MLP)

– SF = SO16 (300 mils body width)

– SE = SO8W (SO8 208 mils body width)

May 2011

Micron Technology, Inc., reserves the right to change products or specifications without notice.

retfa yltcerid edom PiX selbane

Rev 7

no rewop

1/183

Contents

N25Q128 - 3 V

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write protect/enhanced program supply voltage (W/VPP), DQ2 . . . . . . . 18

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1

4.2

4.3

Extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

Extended SPI Protocol Operating features . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.1.8

5.1.9

5.1.10

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 24

Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 24

Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 25

Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2

Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.1

Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

N25Q128 - 3 V

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

Contents

Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 28

Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 28

Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 28

HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3

Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Quad Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

QUAD Command Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 30

Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 30

Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 31

HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

VPP pin Enhanced Supply Voltage feature . . . . . . . . . . . . . . . . . . . . . . 31

Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1

Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

BP3, BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2

Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12) . 37

XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 38

Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 38

Fast POR NV configuration bit (NVCR bit 5) . . . . . . . . . . . . . . . . . . . . . 38

Hold (Reset) disable NV configuration bit (NVCR bit 4) . . . . . . . . . . . . 38

Quad Input NV configuration bit (NVCR bit 3) . . . . . . . . . . . . . . . . . . . . 39

Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 39

6.3

Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.1

6.3.2

Dummy clock cycle: VCR bits 7 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 42

6.4

Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 42

3/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Contents

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

N25Q128 - 3 V

Quad Input Command VECR<7> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Dual Input Command VECR<6> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Reset/Hold disable VECR<4> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3> . . . 44

Output Driver Strength VECR<2:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5

Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

6.5.6

6.5.7

P/E Controller Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Erase Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Erase Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Program Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

VPP Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Program Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Protection Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.1

7.2

SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . . 49

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.1

Extended SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.1.7

9.1.8

9.1.9

9.1.10

9.1.11

9.1.12

9.1.13

9.1.14

9.1.15

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . 82

Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Dual I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Quad Output Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Quad I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

N25Q128 - 3 V

9.1.16

9.1.17

9.1.18

9.1.19

9.1.20

9.1.21

9.1.22

9.1.23

9.1.24

9.1.25

9.1.26

9.1.27

9.1.28

9.1.29

9.1.30

9.1.31

9.1.32

9.1.33

Contents

Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 111

Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 111

9.2

DIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.2.8

9.2.9

9.2.10

9.2.11

9.2.12

9.2.13

9.2.14

9.2.15

9.2.16

9.2.17

9.2.18

Multiple I/O Read Identification protocol . . . . . . . . . . . . . . . . . . . . . . . 114

Dual Command Fast Read (DCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Dual Command Page Program (DCPP) . . . . . . . . . . . . . . . . . . . . . . . 117

Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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Electrical schematic circuit of M7120A horizontal axis giant table surface grinder with improved precision

Single-phase half-wave rectifier capacitor filter circuit

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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