33C408
4 Megabit (512K x 8-Bit)
CMOS SRAM
Memory
Logic Diagram
F
EATURES
:
• R
AD
-P
AK
® Technology radiation-hardened
against natural space radiation
• 524,288 x 8 bit organization
· Total dose hardness:
- > 100 krad (Si), depending upon space mis-
sion
• Excellent Single Event Effect
·
- SEL
TH
: > 68 MeV/mg/cm
2
· - SEU
TH
: = 3 MeV/mg/cm
2
•
- SEU saturated cross section: 6E-9 cm
2
/bit
Package:
- 32-Pin R
AD
-P
AK
® flat pack
- 32-Pin Non-R
AD
-P
AK
® flat pack
Fast access time:
- 20, 25, 30 ns maximum times available
Single 5V + 10% power supply
Fully static operation
- No clock or refresh required
Three state outputs
TTL compatible inputs and outputs
Low power:
- Standby: 60 mA (TTL); 10 mA (CMOS)
- Operation: 180 mA (20 ns); 170 mA (25 ns);
160 mA (30 ns)
D
ESCRIPTION
:
Maxwell Technologies’ 33C408 high-density 4
Megabit SRAM microcircuit features a greater than
100 krad (Si) total dose tolerance, depending upon
space mission. Using Maxwell’s radiation-hard-
ened R
AD
-P
AK
® packaging technology, the 33C408
realizes a high density, high performance, and low
power consumption. Its fully static design elimi-
nates the need for external clocks, while the
CMOS circuitry reduces power consumption and
provides higher reliability. The 33C408 is equipped
with eight common input/output lines, chip select
and output enable, allowing for greater system flex-
ibility and eliminating bus contention. The 33C408
features the same advanced 512K x 8-bit SRAM,
high-speed, and low-power demand as the com-
mercial counterpart.
Maxwell Technologies' patented R
AD
-P
AK
packag-
ing technology incorporates radiation shielding in
the microcircuit package. It eliminates the need for
box shielding while providing the required radiation
shielding for a lifetime in orbit or space mission. In
a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is
available with screening up to Class S.
•
•
•
•
•
•
04.16.02 REV 8
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
33C408
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
12-5, 27, 26, 23, 25, 4,
28, 3, 31, 2, 30, 1
29
22
24
13-15, 17-21
32
16
S
YMBOL
A0-A18
WE
CS
OE
I/O 1-I/O 8
V
CC
V
SS
D
ESCRIPTION
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power (+5.0V)
Ground
T
ABLE
2. 33C408 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Voltage on V
CC
supply relative to V
SS
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
S
YMBOL
V
CC
V
IN
, V
OUT
P
D
T
S
T
A
M
IN
-0.5
-0.5
--
-65
-55
M
AX
7.0
V
CC
+0.5
1.0
+150
+125
U
NIT
V
V
W
°
C
°
C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC1
I
SB
I
SB1
I
LI
V
ARIATION
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
04.16.02 REV 8
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
4. 33C408 R
ECOMMENDED
O
PERATING
C
ONDITIONS
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Supply Voltage
Ground
Input High Voltage
1
Input Low Voltage
2
Thermal Impedance
1. V
IH
(max) = V
CC
+2.0V ac (pulse width < 10 ns) for I < 20 mA
2.
V
IL
(min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA
S
YMBOL
V
CC
V
SS
V
IH
V
IL
M
IN
4.5
0
2.2
-0.5
--
M
AX
5.5
0
33C408
U
NIT
V
V
V
V
°C/W
V
CC
+0.5
0.8
1.21
Θ
JC
T
ABLE
5. 33C408 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Current
-20
-25
-30
Standby Power
Supply Current
CMOS Standby Power
Supply Current
Input Capacitance
1
Output Capacitance
1
1. Guaranteed by design.
S
YMBOL
I
LI
I
LO
V
OL
V
OH
I
CC
C
ONDITION
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
,
V
OUT
=V
SS
to V
CC
I
OL
= 8mA
I
OH
= -4mA
Min cycle, 100% Duty, CS=V
IL
, I
OUT
=0mA,
V
IN
= V
IH
or V
IL
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
--
--
--
1, 2, 3
1, 2, 3
--
--
180
170
160
60
10
mA
mA
M
IN
-2
-2
--
2.4
M
AX
2
2
0.4
--
U
NIT
µA
µA
V
V
mA
I
SB
I
SB1
CS = V
IH
, Min Cycle
CS > V
CC
- 0.2V, f = 0 MHz, V
IN
> V
CC
- 0.2V
or
V
IN <
0.2V
V
IN
= 0V, f = 1MHz, T
A
= 25 °C
V
I/O
= 0V
C
IN
C
I/O
1, 2, 3
4, 5, 6
--
--
7
8
pF
pF
T
ABLE
6. 33C408 AC T
EST
C
ONDITIONS AND
C
HARACTERISTICS
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Pulse Level
Output Timing Measurement Reference Level
04.16.02 REV 8
M
IN
0.0
--
T
YP
--
--
M
AX
3.0
1.5
U
NITS
V
V
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
6. 33C408 AC T
EST
C
ONDITIONS AND
C
HARACTERISTICS
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Rise/Fall Time
Input Timing Measurement Reference Level
M
IN
--
--
T
YP
--
--
M
AX
3.0
1.5
33C408
U
NITS
ns
V
T
ABLE
7. 33C408 AC C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 5V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Read Cycle Time
-20
-25
-30
Address Access Time
-20
-25
-30
Chip Select Access Time
-20
-25
-30
Output Enable to Output Valid
-20
-25
-30
Chip Enable to Output in Low-Z
-20
-25
-30
Output Enable to Output in Low-Z
-20
-25
-30
Chip Deselect to Output in High-Z
-20
-25
-30
Output Disable to Output in High-Z
-20
-25
-30
Output Hold from Address Change
-20
-25
-30
S
YMBOL
t
RC
S
UBGROUPS
9, 10, 11
20
25
30
t
AA
9, 10, 11
--
--
--
t
CO
9, 10, 11
--
--
--
t
OE
9, 10, 11
--
--
--
t
LZ
9, 10, 11
--
--
--
t
OLZ
9, 10, 11
--
--
--
t
HZ
9, 10, 11
--
--
--
t
OHZ
9, 10, 11
--
--
--
t
OH
9, 10, 11
3
5
6
04.16.02 REV 8
M
IN
T
YP
--
--
--
--
--
--
--
--
--
--
--
--
3
3
3
0
0
0
5
6
8
5
6
8
--
--
--
M
AX
--
--
--
U
NIT
ns
ns
20
25
30
ns
20
25
30
10
12
14
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
ns
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
7. 33C408 AC C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 5V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Chip Select to Power Up Time
-20
-25
-30
Chip Select to Power Down Time
-20
-25
-30
S
YMBOL
t
PU
S
UBGROUPS
9, 10, 11
--
--
--
t
PD
9, 10, 11
--
--
--
10
15
20
0
0
0
M
IN
T
YP
33C408
M
AX
--
--
--
ns
--
--
--
U
NIT
ns
T
ABLE
8. 33C408 F
UNCTIONAL
D
ESCRIPTION
CS
H
L
L
L
1. X = don’t care.
WE
X
1
H
H
L
OE
X
1
H
L
X
1
M
ODE
Not Select
Output Disable
Read
Write
I/O P
IN
High-Z
High-Z
D
OUT
D
IN
S
UPPLY
C
URRENT
I
SB
, I
SB1
I
CC
I
CC
I
CC
Subgroups
T
ABLE
9. 33C408 AC C
HARACTERISTICS FOR
W
RITE
C
YCLE
(V
CC
= 5V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Write Cycle Time
-20
-25
-30
Chip Select to End of Write
-20
-25
-30
Address Setup Time
-20
-25
-30
Address Valid to End of Write
-20
-25
-30
S
UBGROUPS
9, 10, 11
S
YMBOL
t
WC
20
25
30
9, 10, 11
t
CW
14
15
17
9, 10, 11
t
AS
0
0
0
9, 10, 11
t
AW
14
15
17
--
--
--
--
--
--
--
--
--
--
--
--
ns
--
--
--
--
--
--
ns
--
--
--
--
--
--
ns
M
IN
T
YP
M
AX
U
NIT
ns
04.16.02 REV 8
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
Power technology
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