SCG4501
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Features
• ± 32 ppm Capture/Pull-In Range
• Phase Locked Output Frequency Control
• Intrinsically Low Jitter Crystal Oscillator
• LVPECL Outputs with Disable Function
• Dual Input References
• LOR & LOL combined alarm output
• Force Free Run Function
• Automatic Free Run operation on loss of
both References A & B
• Input Duty Cycle Tolerant
Bulletin
Page
Revision
Date
Issued By
SG040
1 of 16
P01
13 NOV 03
MBatts
• 3.3V dc Power Supply
• Small Size: 1 Square Inch
General Description
The SCG4501 is a mixed-signal phase locked loop
generating LVPECL outputs from an intrinsically low
jitter, voltage controlled, crystal oscillator. The LVPECL
outputs may be disabled.
The SCG4501 can lock to one of two external
references, which is selectable using the SEL
AB
input
select pin. The unit has a fast acquisition time of about
1.5 seconds and it is tolerant of different reference duty
cycles.
The SCG4501 includes an alarm output that
indicates deviations from normal operation. If a Loss-
of-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FR
status
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to ±20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1” x 1.025” x .45” on a
6 layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Maximum Dimension Package Outline
Figure 1
Block Diagram
Figure 2
10 kΩ
FORCE
FREE RUN
33
Ω
FREE RUN STATUS
10 kΩ
ALARM
Q
QN
REFA
REFB
33
Ω
8 KHz PHASE
ALIGNER
DPFD
ANALOG
FILTER
LOW JITTER
VCXO
SEL AB
10 kΩ
1/N
33
Ω
ENABLE/
TRI-STATE
10 kΩ
OPTIONAL
REFERENCE
OUTPUT
Absolute Maximum Rating
Table 1
Symbol
V
cc
V
i
T
s
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Minimum
-0.5
-0.5
-65.0
Nominal
-
-
-
Maximum
+4.0
+5.5
+100
Units
Volts
Volts
°C
Notes
1.0
1.0
1.0
Preliminary Data Sheet #:
SG040
Page 2
of
16
Rev:
P01
Date:
11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Operating Specifications
Table 2
Symbol
V
cc
I
cc
T
o
F
fr
F
cap
F
bw
T
jtol
T
aq
Parameter
Power Supply Voltage
Power Supply Current
Temperature Range
Free Run Frequency
Capture/pull-in range
Jitter Filter Bandwidth
Input Jitter Tolerance
(Input Jitter Frequencies
≥
10 Hz)
Minimum
3.135
170
0
-20
-32
-
31.25
1
Nominal
3.3
230
-
-
-
-
-
-
Maximum
3.465
280
70
20
32
10
-
-
Units
Volts
mA
°C
ppm
ppm
Hz
µs
µs
Notes
2.0
4.0
3.0
8 kHz Ref. units
19.44 MHz Ref. units
Typical Acquisition Time Data
Acquisition from a cold power-up:
Phase lock within 12ns:
50
sec
Phase lock settled:
220
sec
Alarm time:
<1.5
sec
Acquisition from Free Run:
Phase lock within 12ns:
50
sec
Phase lock settled:
220
sec
Alarm time:
Typically no alarm
Frequency lock with a 20PPM reference frequency step: Typically 0.5s.
Phase lock during a switch between equal frequency references: Typically 0.5s, no alarm should be issued
T
rf
DC
MTIE
sr
Output Rise and Fall Time (20% 80%)
Output Duty Cycle
MTIE at Synchronization Rearrangement
Dynamic Offset Range (0°- 25°)
Dynamic Offset Range (25°- 70°)
-50
-50
100
40
225
50
-
-
350
60
50
50
ps
%
5.0, 6.0
ns
ns
4.0
GR-253-CORE.1999 R5-136
Output Jitter Specifications
Table 3
Frequency (MHz)
77.76
125.00
155.52
Jitter BW 10 Hz - 1 MHz
pS (RMS)
m UI
10 Typ.
10 Typ.
10 Typ.
0.776 Typ.
1.250 Typ.
1.556 Typ.
SONET Jitter BW 12 kHz - 20 MHz
pS (RMS)
m UI
1 Max.
1 Max.
1 Max.
0.076 Max.
0.125 Max.
0.156 Max.
NOTES:
1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF)
3.0 3db loop response.
4.0 50-ohm load biased to 1.3 volts.
5.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing.
6.0 If the selected reference is removed system response to the ALARM must be less than 10µs.
Preliminary Data Sheet #:
SG040
© Copyright 2003 The Connor-Winfield Corp.
Page 3
of
16
Rev:
P01
Date:
11/13/03
All Rights Reserved
Specifications subject to change without notice
Input And Output Characteristics
Table 4
Symbol
Parameter
Minimum
2.0
0.0
-
-
2.4
-
12.5
2.27
1.49
-
-
Nominal
-
-
-
-
-
-
-
2.34
1.51
-
50
Maximum
5.5
0.8
10
10
-
0.4
-
2.52
1.68
10
-
Units
V
V
ns
pF
V
V
ns
V
V
pF
ps
Notes
CMOS Input and Output Characteristics
V
ih
High Level Input Voltage
V
il
T
io
C
l
V
oh
V
ol
T
ir
Low Level Input Voltage
I/O to Output Valid
Output Capacitance
High Level Output Voltage
Low Level Output Voltage
Input Reference Pulse Width
PECL Output Characteristics
V
oh
High Level PECL Voltage
V
ol
C
l
T
skew
Low Level PECL Voltage
Output Capacitance
Differential Output Skew
Input Selection / Output Response
Table 5
RESET
1
X
0
0
0
0
0
0
0
0
ENABLE
0
1
0
0
0
0
0
0
0
0
SEL
AB
X
X
X
0
1
0
1
1
0
X
INPUTS
REF
A
X
X
X
A
A
NA
NA
A
A
NA
REF
B
X
X
X
A
A
A
A
NA
NA
NA
FR
X
X
1
0
0
0
0
0
0
0
FR
status
1
X
1
0
0
0
0
0
0
1
OUTPUTS
ALARM
X
X
X
0
0
1
0
1
0
1
NOTE
Q
X
0
X
X
X
X
X
X
X
X
QN
X
1
X
X
X
X
X
X
X
X
FR
RA
RB
U
RB
U
RA
FR
FR
NOTES:
A
Active
FR Free Run Mode
NA Not Active
RA Locked to Reference A
RB Locked to Reference B
U
Unstable (due to conditions shown, switch to active reference or Free Run)
X
Don’t care
Preliminary Data Sheet #:
SG040
Page 4
of
16
Rev:
P01
Date:
11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Typical MTIE Measurement
Figure 3
Typical TDEV Measurement
Figure 4
Preliminary Data Sheet #:
SG040
© Copyright 2003 The Connor-Winfield Corp.
Page 5
of
16
Rev:
P01
Date:
11/13/03
All Rights Reserved
Specifications subject to change without notice
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