K4H510438D
K4H510838D
K4H511638D
DDR SDRAM
512Mb D-die DDR SDRAM Specification
60 FBGA with Pb-Free
(RoHS compliant)
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
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* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 March 2006
K4H510438D
K4H510838D
K4H511638D
DDR SDRAM
Table of Contents
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ...................................................................................................................4
3.0 Operating Frequencies................................................................................................................4
4.0 Pin Description ...........................................................................................................................5
5.0 Package Physical Dimension ....................................................................................................6
6.0 Block Diagram (32Mbit x4 / 16Mbit x8 / 8Mbit x16 I/O x4 Banks).............................................7
7.0 Input/Output Function Description ............................................................................................8
8.0 Command Truth Table.................................................................................................................9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0 DDR SDRAM IDD Spec Items & Test Conditions ..................................................................11
13.0 Input/Output Capacitance ......................................................................................................11
14.0 Detailed Test Condition for DDR SDRAM IDD1 & IDD7A ....................................................12
15.0 DDR SDRAM IDD Spec Table .................................................................................................13
16.0 AC Operating Conditions .......................................................................................................14
17.0 AC Overshoot/Undershoot Specification for Address and Control Pins ..........................14
18.0 Overshoot/Undershoot Specification for Data, Strobe and Mask Pins ..............................15
19.0 AC Timming Parameters & Specifications ...........................................................................16
20.0 System Characteristics for DDR SDRAM ..............................................................................17
21.0 Component Notes ....................................................................................................................18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.0 March 2006
K4H510438D
K4H510838D
K4H511638D
DDR SDRAM
Year
2006
- First release, revision 1.0 SPEC
History
Revision History
Revision
1.0
Month
March
Rev. 1.0 March 2006
K4H510438D
K4H510838D
K4H511638D
DDR SDRAM
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA
Pb-Free
package
•
RoHS compliant
2.0 Ordering Information
Part No.
K4H510438D-ZC/LCC
K4H510438D-ZC/LB3
K4H510838D-ZC/LCC
K4H510838D-ZC/LB3
K4H511638D-ZC/LCC
K4H511638D-ZC/LB3
Org.
128M x 4
64M x 8
32M x 16
Max Freq.
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Interface
SSTL2
SSTL2
SSTL2
Package
60ball FBGA
60ball FBGA
60ball FBGA
3.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
Rev. 1.0 March 2006
K4H510438D
K4H510838D
K4H511638D
DDR SDRAM
4.0 Ball Description
(Top
View)
128M x 4
9
8
7
3
2
1
VDDQ
NC
VDD
A
VSS
NC
VSSQ
NC
VSSQ
DQ0
B
DQ3
VDDQ
NC
NC
VDDQ
NC
C
NC
VSSQ
NC
NC
VSSQ
DQ1
D
DQ2
VDDQ
NC
NC
VDDQ
NC
E
DQS
VSSQ
NC
NC
VDD
NC
F
DM
VSS
VREF
CAS
WE
G
CK
CK
CS
RAS
H
CKE
A12
BA0
BA1
J
A9
A11
A10/AP
A0
K
A7
A8
A1
A2
L
A5
A6
A3
VDD
M
VSS
A4
64M x 8
9
8
7
3
2
1
VDDQ
DQ0
VDD
A
VSS
DQ7
VSSQ
NC
VSSQ
DQ1
B
DQ6
VDDQ
NC
NC
VDDQ
DQ2
C
DQ5
VSSQ
NC
NC
VSSQ
DQ3
D
DQ4
VDDQ
NC
NC
VDDQ
NC
E
DQS
VSSQ
NC
NC
VDD
NC
F
DM
VSS
VREF
CAS
WE
G
CK
CK
CS
RAS
H
CKE
A12
BA0
BA1
J
A9
A11
A10/AP
A0
K
A7
A8
A1
A2
L
A5
A6
A3
VDD
M
VSS
A4
32M x 16
9
8
7
3
2
1
VDDQ
DQ0
VDD
A
VSS
DQ15
VSSQ
DQ1
VSSQ
DQ2
B
DQ13
VDDQ
DQ14
DQ3
VDDQ
DQ4
C
DQ11
VSSQ
DQ12
DQ5
VSSQ
DQ6
D
DQ9
VDDQ
DQ10
DQ7
VDDQ
LDQS
E
UDQS
VSSQ
DQ8
NC
VDD
LDM
F
UDM
VSS
VREF
CAS
WE
G
CK
CK
CS
RAS
H
CKE
A12
BA0
BA1
J
A9
A11
A10/AP
A0
K
A7
A8
A1
A2
L
A5
A6
A3
VDD
M
VSS
A4
Organization
128Mx4
64Mx8
32Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11, A12
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.0 March 2006