®
ST7FLCD1
8-bit MCU for LCD Monitors with 60 KBytes Flash,
2 KBytes RAM, 2 DDC Ports and Infrared Controller
Key Features
■
60 KBytes Flash Program Memory
■
In-Circuit Debugging and Programming
■
In-Application Programming
■
Data RAM: up to 2 KBytes (256 bytes stack,
2 x 256 bytes for DDCs)
■
8 MHz, up to 9 MHz Internal Clock Frequency
■
True Bit Manipulation
■
Run and Wait CPU Modes
■
Programmable Watchdog for System
Reliability
■
Protection against Illegal Opcode Execution
■
2 DDC Bus Interfaces with:
●
●
●
●
SO28
ORDER CODE: ST7FLCD1
General Description
The ST7FLCD1 is a microcontroller (MCU) from the
ST7 family with dedicated peripherals for LCD
monitor applications. The ST7FLCD1 is an industry
standard 8-bit core that offers an enhanced
instruction set. The 5V supplied processor runs
with an external clock at 24 MHz (27 MHz
maximum). Under software control, the MCU mode
changes to Wait mode thus reducing power
consumption. The enhanced instruction set and
addressing modes offer real programming
potential.
In addition to standard 8-bit data management, the
MCU features also include true bit manipulation,
8x8 unsigned multiplication and indirect addressing
modes.
The device gathers the on-chip oscillator, CPU,
60-Kbyte Flash, 2-KByte RAM, I/Os, two 8-bit
timers, infrared preprocessor, 4-channel Analog-to-
Digital Converter, 2 DDCs, I²C single master,
watchdog, reset and six 8-bit PWM outputs for
analog DC control of external functions.
DDC 2B protocol implemented in hardware
Programmable DDC CI modes
Enhanced DDC (EDDC) address decoding
HDCP Encryption keys
■
Fast I²C Single Master Interface
■
8-bit Timer with Programmable Pre-scaler,
Auto-reload and independent Buzzer Output
■
8-bit Timer with External Trigger
■
4-channel, 8-bit Analog to Digital Converter
■
4 + 2 8-bit PWM Digital to Analog Outputs
with Frequency Adjustment
■
Infrared Controller (IFR)
■
Up to 22 I/O Lines in 28-pin Package
■
2 Lines Programmable as Interrupt Inputs
■
Master Reset and Low Voltage Detector (LVD)
Reset
■
Complete Development Support on PC-
Windows
■
Full Software Package (Assembler, Linker,
C-compiler and Source Level Debugger)
February 2005
Revision 2.10
eDocs No. CD00003537
1/95
ST7FLCD1
Table of Contents
Chapter 1
1.1
1.2
1.3
1.4
1.5
1.6
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Diagram ..................................................................................................................... 6
Abbreviations ....................................................................................................................... 6
Reference Documents ......................................................................................................... 7
Pin Description .................................................................................................................... 8
External Connections ......................................................................................................... 10
Memory Map ..................................................................................................................... 11
Chapter 2
2.1
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Main Features .................................................................................................................... 15
2.1.1
CPU Registers ...................................................................................................................................15
Chapter 3
3.1
3.2
3.3
3.4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Low Voltage Detector and Watchdog Reset ...................................................................... 22
Watchdog or Illegal Opcode Access Reset ........................................................................ 23
External Reset .................................................................................................................... 23
Reset Procedure ................................................................................................................ 23
Chapter 4
4.1
4.2
4.3
4.4
4.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Software ............................................................................................................................. 24
External Interrupts (ITA, ITB) ............................................................................................. 24
Peripheral Interrupts ........................................................................................................... 24
Processing ......................................................................................................................... 24
Register Description .......................................................................................................... 26
Chapter 5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Introduction ........................................................................................................................ 28
Main Features .................................................................................................................... 28
Structure ............................................................................................................................. 28
Program Memory Read-out Protection .............................................................................. 28
In-Circuit Programming (ICP) ............................................................................................. 29
In-Application Programming (IAP) ...................................................................................... 30
Register Description ........................................................................................................... 30
Flash Option Bytes ............................................................................................................. 31
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ST7FLCD1
Chapter 6
6.1
Clocks & Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Clock System ..................................................................................................................... 32
6.1.1
6.1.2
6.1.3
6.1.4
General Description ...........................................................................................................................32
Crystal Oscillator Mode ......................................................................................................................32
External Clock Mode ..........................................................................................................................32
Clock Signals .....................................................................................................................................33
6.2
Power Saving Modes ......................................................................................................... 33
6.2.1
6.2.2
6.2.3
6.2.4
HALT Mode ........................................................................................................................................33
WAIT Mode ........................................................................................................................................33
Exit from HALT and WAIT Modes ......................................................................................................33
Selected Peripherals Mode ................................................................................................................34
Chapter 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction ........................................................................................................................ 35
Common Functional Description ........................................................................................ 36
Port A ................................................................................................................................. 37
Port B ................................................................................................................................. 39
Port C ................................................................................................................................. 40
Port D ................................................................................................................................. 41
Register Description ........................................................................................................... 42
Chapter 8
8.1
8.2
8.3
8.4
PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Introduction ........................................................................................................................ 43
Main Features .................................................................................................................... 43
Functional Description ........................................................................................................ 43
Register Description ........................................................................................................... 46
Chapter 9
9.1
9.2
9.3
9.4
8-bit Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction ........................................................................................................................ 49
Main Features .................................................................................................................... 49
Functional Description ........................................................................................................ 49
Register Description ........................................................................................................... 50
Chapter 10
10.1
10.2
10.3
10.4
10.5
I²C Single-Master Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Introduction ........................................................................................................................ 52
Main Features .................................................................................................................... 52
General Description ........................................................................................................... 52
Functional Description (Master Mode) ............................................................................... 54
Transfer Sequencing .......................................................................................................... 54
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ST7FLCD1
10.5.1
10.5.2
Master Receiver .................................................................................................................................54
Master Transmitter .............................................................................................................................54
10.6
Register Description ........................................................................................................... 56
Chapter 11
11.1
11.2
Display Data Channel Interfaces (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Introduction ........................................................................................................................ 60
DDC Interface Features ..................................................................................................... 60
11.2.1
11.2.2
Hardware DDC2B Interface Features ................................................................................................60
DDC/CI Factory Interface Features ....................................................................................................60
11.3
Signal Description .............................................................................................................. 62
11.3.1
11.3.2
Serial Data (SDA) ..............................................................................................................................62
Serial Clock (SCL) .............................................................................................................................62
11.4
DDC Standard .................................................................................................................... 62
11.4.1
11.4.2
DDC2B Interface ................................................................................................................................62
Mode Description ...............................................................................................................................63
11.5
11.6
11.7
DDC/CI Factory Alignment Interface .................................................................................. 66
11.5.1
I²C Modes ..........................................................................................................................................66
Transfer Sequencing .......................................................................................................... 68
Register Description ........................................................................................................... 69
Chapter 12
12.1
12.2
12.3
12.4
12.5
12.6
Watchdog Timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Introduction ........................................................................................................................ 75
Main Features .................................................................................................................... 75
Main Watchdog Counter .................................................................................................... 75
Lock-up Counter ................................................................................................................. 76
Interrupts ............................................................................................................................ 76
Register Description ........................................................................................................... 76
Chapter 13
13.1
13.2
13.3
13.4
8-bit Timer (TIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Introduction ........................................................................................................................ 77
Main Features .................................................................................................................... 77
Functional Description ........................................................................................................ 77
Register Description ........................................................................................................... 78
Chapter 14
14.1
14.2
14.3
8-bit Timer with External Trigger (TIMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Introduction ........................................................................................................................ 80
Main Features .................................................................................................................... 80
Functional Description ........................................................................................................ 80
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ST7FLCD1
Chapter 15
15.1
15.2
15.3
Infrared Preprocessor (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Main Features .................................................................................................................... 83
Functional Description ........................................................................................................ 83
Register Description ........................................................................................................... 84
Chapter 16
16.1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Register Description ........................................................................................................... 85
Chapter 17
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Absolute Maximum Ratings .............................................................................................. 87
Power Considerations ........................................................................................................ 87
Thermal Characteristics .................................................................................................... 88
AC/DC Electrical Characteristics ........................................................................................ 88
Power On/Off Electrical Specifications ............................................................................... 90
8-bit Analog-to-Digital Converter ....................................................................................... 90
I2C/DDC Bus Electrical Specifications .............................................................................. 91
I2C/DDC Bus Timings ....................................................................................................... 91
Chapter 18
Chapter 19
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
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Analogue and Mixed Signal
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