K6X1008C2D Family
Document Title
128Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
0.1
History
Initial draft
Revised
- Deleted 32-TSOP1-0820R Package Type.
- Added Commercial product.
Revised
- Added Lead Free 32-SOP-525 Product
Revised
- Added Lead Free 32-TSOP1-0820F Product
Finalized
- Changed I
CC
from 10mA to 5mA
- Changed I
CC
2 from 35mA to 25mA
- Changed I
SB
from 3mA to 0.4mA
- Changed I
DR
(industrial)
from 15µA to 10µA
- Changed I
DR
(Automotive)
from 25µA to 20µA
Draft Data
July 15, 2002
December 4, 2002
Remark
Preliminary
Preliminary
0.2
May 13, 2003
Preliminary
0.3
June 21, 2003
Preliminary
1.0
September 16, 2003
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
September 2003
K6X1008C2D Family
128Kx8 bit Low Power full CMOS Static RAM
FEATURES
•
Process Technology: Full CMOS
•
Organization: 128K x 8
•
Power Supply Voltage: 4.5~5.5V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-DIP-600, 32-SOP-525,
32-SOP-525, 32-TSOP1-0820F
CMOS SRAM
GENERAL DESCRIPTION
The K6X1008C2D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
verious operating temperature ranges and have various pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
PRODUCT FAMILY
Product Family
K6X1008C2D-B
K6X1008C2D-F
K6X1008C2D-Q
Operating
Temperature
Commercial(0~70°C)
Industrial(-40~85°C)
Automotive(-40~125°C)
4.5~5.5V
55
1)
/70ns
Power Dissipation
Vcc Range
Speed
Standby
(I
SB1
, Max)
10µA
15µA
25µA
25mA
Operating
(I
CC2,
Max)
PKG Type
32-DIP-600, 32-SOP-525,
32-SOP-525
32-TSOP1-0820F
32-SOP-525, 32-TSOP1-0820F
1. The parameters are tested with 50pF test load
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-SOP
32-DIP
27
26
25
24
23
22
21
20
19
18
17
Row
addresses
Row
select
Memory array
32-TSOP
Type1-Forward
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
Column Addresses
Name
CS
1
, CS
2
OE
WE
I/O
1
~I/O
8
A
0
~A
16
Vcc
Vss
NC
Function
Chip Select Input
Output Enable Input
Write Enable Input
Data Inputs/Outputs
Address Inputs
Power
Ground
No Connection
CS
1
CS
2
WE
OE
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.0
September 2003
K6X1008C2D Family
PRODUCT LIST
Commercial Products(0~70°C)
Part Name
K6X1008C2D-DB55
K6X1008C2D-DB70
K6X1008C2D-GB55
K6X1008C2D-GB70
K6X1008C2D-BB55
1)
K6X1008C2D-BB70
1)
K6X1008C2D-TB55
K6X1008C2D-TB70
K6X1008C2D-PB55
1)
K6X1008C2D-PB70
1)
1. Lead Free Product
CMOS SRAM
Industrial Products(-40~85°C)
Part Name
K6X1008C2D-DF55
K6X1008C2D-DF70
K6X1008C2D-GF55
K6X1008C2D-GF70
K6X1008C2D-BF55
1)
K6X1008C2D-BF70
1)
K6X1008C2D-TF55
K6X1008C2D-TF70
K6X1008C2D-PF55
1)
K6X1008C2D-PF70
1)
Automotive Products(-40~125°C)
Part Name
K6X1008C2D-GQ55
K6X1008C2D-GQ70
K6X1008C2D-TQ55
K6X1008C2D-TQ70
Function
32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
Function
32-DIP, 55ns, LL
32-DIP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-SOP, 55ns, LL
32-SOP, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
32-TSOP-F, 55ns, LL
32-TSOP-F, 70ns, LL
Function
32-SOP, 55ns, L
32-SOP, 70ns, L
32-TSOP-F, 55ns, L
32-TSOP-F, 70ns, L
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to V
CC+
0.5V(Max. 7.0V)
-0.3 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
-40 to 125
Unit
V
V
W
°C
°C
°C
°C
Remark
-
-
-
-
K6X1008C2D-B
K6X1008C2D-F
K6X1008C2D-Q
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
September 2003
K6X1008C2D Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
4.5
0
2.2
-0.5
3)
Typ
5.0
0
-
-
CMOS SRAM
Max
5.5
0
Vcc+0.5
2)
0.8
Unit
V
V
V
V
Note:
1. Commercial Product: T
A
=0 to 70°C, Otherwise specified
Industrial Product: T
A
=-40 to 85°C, Otherwise specified
Automotive Product: T
A
=-40 to 125°C, Otherwise specified
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1
)
(f=1MHz, TA=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
, Read
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or
CS
2
≤0.2V,
Other inputs=0~Vcc
K6X1008C2D-B
K6X1008C2D-F
K6X1008C2D-Q
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
5
7
25
0.4
-
0.4
10
15
25
µA
µA
mA
mA
mA
V
V
mA
µA
µA
µA
4
Revision 1.0
September 2003
K6X1008C2D Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(V
CC
=4.5~5.5V, Commercial product: T
A
=0 to 70°C, Industrial product: T
A
=-40 to 85°C, Automotive product: T
A
=-40~125°C
)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Read
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
20
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
25
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Symbol
V
DR
I
DR
CS
1
≥Vcc-0.2V
1)
K6X1008C2D-B
Vcc=3.0V,
CS
1
≥Vcc-0.2V
1)
K6X1008C2D-F
K6X1008C2D-Q
Data retention set-up time
Recovery time
t
SDR
t
RDR
See data retention waveform
Test Condition
Min
2.0
-
-
-
0
5
Typ
-
-
-
-
-
-
Max
5.5
10
10
20
-
-
Unit
V
µA
µA
µA
ms
1. CS
1
≥Vcc-0.2V
,
CS
2
≥V
CC
-0.2V, or CS
2
≤0.2V
5
Revision 1.0
September 2003
京公网安备 11010802033920号
EEWORLD
