K6T1008C2E Family
Document Title
128Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
1.0
History
Design target
Finalize
- Improve t
WP
form 55ns to 50ns for 70ns product.
- Remove 55ns speed bin for industrial product.
Errata correction
Draft Data
October 12, 1998
August 30, 1999
Remark
Preliminary
Final
1.01
December 1, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.01
December 1999
K6T1008C2E Family
128Kx8 bit Low Power CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 128Kx8
•
Power Supply Voltage: 4.5~5.5V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP1-0820F
CMOS SRAM
GENERAL DESCRIPTION
The K6T1008C2E families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
K6T1008C2E-L
K6T1008C2E-B
K6T1008C2E-P
K6T1008C2E-F
1. The parameters are tested with 50pF test load
Operating Temperature
Vcc Range
Speed
Standby
(I
SB1
, Max)
50µA
10µA
Operating
(I
CC2,
Max)
PKG Type
Commercial(0~70°C)
4.5~5.5V
Industrial(-40~85°C)
55
1)
/70ns
32-DIP, 32-SOP
32-TSOP1-0820F
50mA
32-SOP -525
32-TSOP1-0820F
70ns
50µA
15µA
PIN DESCRIPTION
N.C
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
VCC
A15
CS2
A11
A9
A8
A13
A8
WE
A9 CS2
A15
A11 VCC
OE NC
A16
A10 A14
A12
CS1 A7
I/O8 A6
A5
I/O7 A4
WE
A13
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
32-DIP
32-SOP
25
24
23
22
21
20
19
18
17
32-TSOP
Type1-Forward
Raw
Address
Row
select
Memory array
1024 rows
128×8 columns
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Name
CS
1
, CS
2
OE
WE
I/O
1
~I/O
8
A
0
~A
16
Vcc
Vss
N.C.
Function
Chip Select Input
Output Enable Input
Write Enable Input
Data Inputs/Outputs
Address Inputs
Power
Ground
No Connection
CS
1
CS
2
WE
OE
Column Address
Data
cont
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.01
December 1999
K6T1008C2E Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
K6T1008C2E-DL55
K6T1008C2E-DL70
K6T1008C2E-DB55
K6T1008C2E-DB70
K6T1008C2E-GL55
K6T1008C2E-GL70
K6T1008C2E-GB55
K6T1008C2E-GB70
K6T1008C2E-TB55
K6T1008C2E-TB70
Function
32-DIP, 55ns, Low Power
32-DIP, 70ns, Low Power
32-DIP, 55ns, Low Low Power
32-DIP, 70ns, Low Low Power
32-SOP, 55ns, Low Power
32-SOP, 70ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Low Power
32-TSOP F, 55ns, Low Low Power
32-TSOP F, 70ns, Low Low Power
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
K6T1008C2E-GP70
K6T1008C2E-GF70
K6T1008C2E-TF70
Function
32-SOP, 70ns, Low Power
32-SOP, 70ns, Low Low Power
32-TSOP F, 70ns, Low Low Power
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
Remark
-
-
-
-
K6T1008C2E-L/-B
K6T1008C2E-P/-F
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.01
December 1999
K6T1008C2E Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
K6T1008C2E Family
All Family
K6T1008C2E Family
K6T1008C2E Family
Min
4.5
0
2.2
-0.5
3)
CMOS SRAM
Typ
5.0
0
-
-
Max
5.5
0
Vcc+0.5
2)
0.8
Unit
V
V
V
V
Note:
1. Commercial Product: T
A
=0 to 70°C, and Industrial Product: T
A
=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1
)
(f=1MHz, TA=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
6
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
, Read
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.4
-
-
-
-
-
-
-
-
-
-
-
1
1
10
7
50
0.4
-
3
50
1)
µA
µA
mA
mA
mA
V
V
mA
µA
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
1. 50µA for Low power product, in case of Low Low power products are comercial=10µA, industrial=15µA.
4
Revision 1.01
December 1999
K6T1008C2E Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
C
L
=50pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(V
CC
=4.5~5.5V, Commercial Product : T
A
=0 to 70°C, Industrial Product : T
A
=-40 to 85°C
)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
20
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
25
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
V
DR
CS
1
≥Vcc-0.2V
1)
K6T1008C2E-L
Data retention current
I
DR
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
K6T1008C2E-B
K6T1008C2E-P
K6T1008C2F-F
Data retention set-up time
Recovery time
t
SDR
t
RDR
See data retention waveform
Test Condition
Min
2.0
-
-
-
-
0
5
Typ
-
-
-
-
-
-
-
Max
5.5
20
10
25
10
-
-
ms
µA
Unit
V
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
5
Revision 1.01
December 1999
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