Ordering number: EN 6158
CMOS IC
LC7940YD,7941YD
Dot-matrix LCD Drivers
Overview
The LC7940YD and LC7941YD are segment driver ICs
for driving large, dot
–
matrix LCD displays. They read 4
–
bit parallel or serial input, display data from a controller
into an 80
–
bit latch, and then generate LCD drive signals
corresponding to that data.
The LC7940YD and LC7941YD feature mirror
–
image pin
assignments, allowing them to be used together to increase
component density. They are designed to be used with the
LC7942YD common driver to drive large LCD panels.
Package Dimensions
unit: mm
3180
–
QIP100D
[LC7940YD, LC7941YD]
23.2
20.0
0.825
0.575
80
81
1.6
0.3
51
50
0.65
0.15
17.2
14.0
2.15
•
•
21.6
0.8
SANYO : QFP100D (QIP100D)
•
•
Specifications
Absolute Maximum Ratings
at Ta = 25 ± 2°C, V
SS
= 0 V
Parameter
Logic supply voltge
LCD supply voltage, See Note below.
Input voltage
Symbol
V
DD
max
V
DD
– V
EE
max
V
I
max
Ratings
–0.3 to +7.0
0 to 22
–0.3 to V
DD
+ 03
Unit
V
V
V
s
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
s
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
63099RM (ID) No. 6158—1/11
0.8
1
30
2.45max
•
•
•
•
80 built
–
in LCD display drive circuits
1/8 to l/128display duty cycle
Serial or 4
–
bit parallel data input
Chip disable for low power dissipation for large
–
sized
panels
Bias supply voltags can be supplied externally
Operating supply voltage and ambient temperature
- 2.7 to 5.5 V logic supply ( V
DD
) at Ta =
–
20 to +85°C
- 8 to 20V LCD supply (V
DD
–
V
EE
) at Ta =
–
20 to
+85 °C
CMOS process
100
–
pin flat plastic package
1.6
31
100
15.6
Features
0.65
LC7940YD, LC7941YD
Parameter
Operating temperature range
Storage temperature range
Symbol
T
opr
T
stg
Ratings
–20 to +85
–40 to +125
Unit
°C
°C
Note
V
DD
≥
V
1
> V
3
> V
4
> V
EE
Recommended Operating Condltions
at Ta =
–
20 to + 85°C, V
SS
= 0V
Ratings
Parameter
Logic supply voltage
LCD supply voltage
HIGH–level input voltage
Symbol
V
DD
V
DD
– V
EE
V
IH
See Notes 1 and 2.
CP, CDl, DI1 to DI3, M,
SDl, P/S, DISPOFF and
LOAD
CP, CDI, Dl1 to DI3, M,
SDl, P/S,DISPOFF and
LOAD
Conditions
min
2.7
8
0.8V
DD
typ
–
–
–
max
5.5
20
–
V
V
V
Unit
LOW–level inpvt voltage
CP shift clock frequency
CP pulsewidth
LOAD pulsewidth
DIn and SDI to CP setup time
DIn and SDI to CP hold time
CP to LOAD time
LOAD to CP time
CP rise time
CP fall time
LOAD rise time
LOAD fall time
V
IL
f
CP
t
WC
t
WL
t
SETUP
t
HOLD
t
CL1
t
CL2
t
LC
t
R
t
F
t
RL
t
FL
–
–
–
0.2V
DD
3.3
–
–
–
–
–
–
–
50
50
50
50
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
100
80
80
0
100
100
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Notes
1. V
DD
≥
V
l
> V
3
> V
4
> V
EE
2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply
should be cut after or simultaneously with the LCD supply.
Electrlcai Characterfstlcs
at Ta = 25 ± 2°C,V
SS
= 0V, V
DD
= 2.7 to 5.5 V
Ratings
Parameter
Symbol
Conditions
min
HIGH–level input current
I
IH
V
IN
=V
DD
; LOAD, CP, CDI,
P/S, DI1 to DI3, SDl, M,
and DISPOFF
V
IN
= V
SS
; LOAD, CP, CDl,
P/S, DI1 to DI3, SDI, M,
and DISPOFF
I
OH
= –400 µA
I
OL
= 400 µA
V
DD
– V
EE
= 18 V,
|V
DE
– V
O
|= 0.25 V.
See note
–
typ
–
max
1
µA
Unit
LOW–level input current
CDO HIGH–level output voltage
CDO LOW–levef output voltage
O1 to O80 driver ON resistance
I
IL
V
OH
V
OL
R
ON
–
V
DD
– 0.4
–
–
–
–
–
2
–1
–
0.4
4
µA
V
V
kΩ
No. 6158—2/11
LC7940YD, LC7941YD
Block Diagram
01
02
03
079 080
V1
V3
V4
V
EE
80
Level Shifter (80 bits)
M
80
2nd Latch (80 bits)
80
1st Latch (80 bits)
4
SDI
DI3
DI2
DI1
4 bits
Data Bus
Interface
CLK
Address Counter
(7 bits)
20
Address Decoder
DISP OFF
4 Level LCD Drive Circuit
(80 bits)
V
DD
V
SS
P/S
CDI
CP
LOAD
SER/PAR
Control
Chip Disable &
Latch Control
CDO
Pin Functions
Pin No.
Synbol
LC7940YD
91
86
87
92
89
88
l00
99
98
97
LC7941YD
90
95
94
89
92
93
81
82
83
84
V
DD
V
SS
V
EE
V
1
V
3
V
4
CP
CDI
LOAD
SDI
I
I
I
I
Supply
LCD panel drive voltage supplies
V
1
and V
EE
are selected levels.
V
3
and V
4
are not–selected levels.
Display data Input clock (falling–edge trigger).
Chip disable.
Data is read in when LOW, and not road in when HIGH.
Display data latch clock (falling–edge trigger).
On the falling edge, the LCD drive signals set by the display data are output.
Serial data input.
Supply
V
DD
– V
SS
is the logic supply.
V
DD
– V
EE
is the LCD supply.
I/O
Functions
No. 6158—5/11
RF/Wirelessly
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