PRELIMINARY
W196
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for 440BX, 440ZX, and
VIA Apollo Pro-133
• I
2
C programmable to 155 MHz (32 selectable
frequencies)
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous w/CPU out-
put)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor
straps on power up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
CPU Cycle to Cycle Jitter: ..........................................250 ps
CPU, PCI Output Edge Rate:.........................................
≥1
V/ns
CPU0:1 Output Skew: ................................................175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA:............... 250-kΩ pull-up
FS1:........................................................... 250-kΩ pull-down
FS0:...................................................No pull-up or pull-down
Note:
Internal pull-up or pull-down resistors should not be re-
lied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
FS1
1
1
0
0
FS0
1
0
1
0
CPU(0:1)
133.3 MHz
105 MHz
100 MHz
66.8 MHz
PCI
33.3 MHz
35 MHz
33.3 MHz
33.3 MHz
Key Specifications
Supply Voltages: ....................................... V
DDQ3
= 3.3V±5%
V
DDQ2
= 2.5V±5%
Block Diagram
VDDQ3
REF2X/SEL48#
GND
X1
X2
XTAL
OSC
PLL Ref Freq
VDDQ3
IOAPIC
Pin Configuration
VDDQ2
CPU0
CPU1
GND
FS1
FS0
PLL 1
÷2/÷3
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24_48MHz/FS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
GND
SDATA
SCLOCK
FS0
GND
SDATA
SCLOCK
I
2
C
LOGIC
PCI5
PCI6
GND
VDDQ3
PLL2
48MHz
24_48MHz/FS1
GND
Cypress Semiconductor Corporation
Document #: 38-07170 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 15, 2002
PRELIMINARY
Pin Definitions
Pin Name
CPU0:1
Pin
No.
22, 21
Pin
Type
O
Pin Description
W196
CPU Clock Outputs 0 through 1:
These two CPU clocks run at a frequency set by
FS0:1 or the serial data interface. See
Table 1
and
Table 5.
Output voltage swing is
set by the voltage applied to VDDQ2.
PCI Bus Clock Outputs 1 through 6 and PCI_F:
These seven PCI clock outputs
run synchronously to the CPU clock. Voltage swing is set by the power connection
to VDDQ3.
I/O APIC Clock Output:
Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48-MHz Output:
Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24-MHz or 48-MHz Output/Frequency Select 1 Input:
Frequency is set by the state
of pin 27 on power-up. This pin doubles as the select strap to determine device
operating frequency as described in
Table 1.
I/O Dual-Function REF2X and SEL48# Pin:
Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to V
DD
. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to V
DD
, pin
14 will output 2 4MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
Frequency Selection 0 Input:
Selects CPU clock frequency as shown in
Table 1
on page 1.
I
2
C Data Pin:
Data should be presented to this input as described in the I
2
C section
of this data sheet. Internal 250-kΩ pull-up resistor.
I
2
C Clock Pin:
The I
2
C Data clock should be presented to this input as described in
the I
2
C section of this data sheet.
Crystal Connection or External Reference Frequency Input:
Connect to either
a 14.318-MHz crystal or other reference signal.
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection:
Power supply for core logic and PLL circuitry, PCI, 48/24MHz,
and Reference output buffers. Connect to 3.3V supply.
Power Connection:
Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.
Ground Connections:
Connect all ground pins to the common system ground
plane.
PCI1:6
PCI_F
IOAPIC
48MHz
24_48MHz/FS1
5, 6, 7, 8, 10,
11, 4
24
13
14
O
O
O
I/O
REF2X/SEL48#
27
I/O
FS0
SDATA
SCLOCK
X1
X2
VDDQ3
VDDQ2
GND
16
18
17
1
2
9, 12, 20, 26
23, 25
3, 15, 19, 28
I
I/O
I
I
I
P
P
G
Document #: 38-07170 Rev. *A
Page 2 of 12
PRELIMINARY
Functional Description
I/O Pin Operation
Pins 14 and 27 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of these pins is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to “0”, connection to V
DD
sets a latch to “1.”
Figure 1
and
Figure 2
show two suggested methods for strapping resistor
connections.
Upon W196 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the REF2X and
24_48MHz clock output buffers are three-stated, allowing the
output strapping resistor on the l/O pin to pull the pin and its
associated capacitive clock load to either a logic HIGH or LOW
state. At the end of the 2-ms period, the established logic “0”
or “1” condition of the l/O pin is then latched. Next the output
W196
buffer is enabled, which converts the l/O pin into an operating
clock output. The 2-ms timer is started when V
DD
reaches
2.0V. The input bits can only be reset by turning V
DD
off and
then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock output is 20Ω (nominal), which is minimally
affected by the 10-kΩ strap to ground or V
DD
. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input pe-
riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If V
DD
has not yet reached
full value, output frequency initially may be below target but will
increase to target once V
DD
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
V
DD
Output Strapping Resistor
Series Termination Resistor
Clock Load
10 kΩ
(Load Option 1)
W196
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Q
Hold
Output
Low
D
10 kΩ
(Load Option 0)
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
Series Termination Resistor
10 kΩ
W196
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Q
V
DD
R
Resistor Value R
Clock Load
Hold
Output
Low
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Document #: 38-07170 Rev. *A
Page 3 of 12
PRELIMINARY
Serial Data Interface
The W196 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W196 initializes
with default register settings. Therefore, the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
Table 2. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Description
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Provides CPU/PCI frequency selections beyond
the selections that are provided by the FS0:1 pins.
Frequency is changed in a smooth and controlled
fashion.
Common Application
W196
chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management func-
tions.
Table 2
summarizes the control functions of the serial
data interface.
Operation
Data is written to the W196 in ten bytes of eight bits each.
Bytes are written in the order shown in
Table 3.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to un-
used PCI slots.
For alternate microprocessors and power man-
agement options. Smooth frequency transition al-
lows CPU frequency change under normal system
operation.
CPU Clock Frequency
Selection
Output Three-state
Test Mode
(Reserved)
Puts all clock outputs into a high-impedance state. Production PCB testing.
All clock outputs toggle in relation to X1 input, in- Production PCB testing.
ternal PLL is bypassed. Refer to
Table 4.
Reserved function for future device revision or pro- No user application. Register bit must be written
duction device testing.
as 0.
Table 3. Byte Writing Sequence
Byte
Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W196 to accept the bits in Data Bytes 3–6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W196 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
Refer to Cypress SDRAM drivers.
2
Command
Code
Don’t Care
3
Byte Count
Don’t Care
4
5
6
7
8
9
10
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Don’t Care
Refer to
Table 4
The data bits in these bytes set internal W196 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to
Table 4,
Data Byte Serial Configuration Map.
Document #: 38-07170 Rev. *A
Page 4 of 12
PRELIMINARY
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7.
Table 4
gives the bit formats for registers located in Data
Bytes 3–6.
Table 4. Data Bytes 3–6 Serial Configuration Map
Affected Pin
Bit(s)
Pin No.
Pin Name
Data Byte 3
7
--
--
6
--
--
5
--
--
4
--
--
3
--
--
Bit Control
Control Function
SEL_3
SEL_2
SEL_1
SEL_0
Frequency Table
Selection
(Reserved)
Bit 1 Bit 0
0
0
0
1
1
0
1
1
0
1
W196
Table 5
details additional frequency selections that are avail-
able through the serial data interface.
Table 6
details the select functions for Byte 3, bits 1 and 0.
Default
0
0
0
0
0
2
1–0
--
--
--
--
Refer to
Table 5
Refer to
Table 5
Refer to
Table 5
Refer to
Table 5
Frequency Controlled Frequency Controlled
by external FS0:1 pins by BYT3 SEL_(3:0)
(Table
1)
Table 5
--
--
Function (See
Table 6
for function details)
Spread Spectrum Off
Test Mode
Spread Spectrum On (default)
All Outputs Three-stated
--
Low
--
--
--
Low
--
Low
Low
Low
Low
--
Low
Low
Low
Low
--
--
Low
--
--
--
Low
Low
--
Active
--
--
--
Active
--
Active
Active
Active
Active
--
Active
Active
Active
Active
--
--
Active
--
--
--
Active
Active
0
10
Data Byte 4
7
6
5
4
3
2
1
0
Data Byte 5
7
6
5
4
3
2
1
0
Data Byte 6
7
6
5
4
3
2
1
0
--
14
--
--
--
21
--
22
4
11
10
-
8
7
6
5
--
--
24
--
--
--
27
27
--
24/48MHz
--
--
--
CPU1
--
CPU0
PCI_F
PCI6
PCI5
--
PCI4
PCI3
PCI2
PCI1
--
--
IOAPIC
--
--
--
REF2X
REF2X
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
0
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
0
1
0
0
0
1
[1]
1
[1]
Note:
1. Bits 0 and 1 of Data Byte 6 in
Table 4
must be programmed as the same value.
Document #: 38-07170 Rev. *A
Page 5 of 12
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