Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
74LVC543A
FEATURES
•
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•
Supply voltage range of 1.2 V to 3.6 V
•
Complies with JEDEC standard no. 8–1A
•
CMOS low power consumption
•
Direct interface with TTL levels
•
8-bit octal transceiver with D-type latch
•
Back-to-back registers for storage
•
Separate controls for data flow in each direction
•
3-State non-inverting outputs for bus oriented applications
•
High impedance when V
CC
= 0 V
DESCRIPTION
The 74LVC543A is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC543A is an octal registered transceiver containing two
sets of D-type latches for temporary storage of the data flow in
either direction. Separate latch enable (LE
AB
, LE
BA
) and output
enable (OE
AB
, OE
BA
) inputs are provided for each register to permit
independent control of inputting and outputting in either direction of
the data flow.
The 74LVC543A contains eight D-type latches, with separate inputs
and controls for each set. For data flow from A to B, for example, the
A-to-B enable (E
AB
) input must be LOW in order to enter data from
A
0
-A
7
or take data from B
0
-B
7
, as indicated in the function table.
With E
AB
LOW, a LOW signal on the A-to-B latch enable (LE
AB
)
input makes the A-to-B latches transparent; a subsequent
LOW–to-HIGH transition of the LE
AB
signal puts the A data into the
latches where it is stored and the B outputs no longer change with
the A inputs. With E
AB
and OE
AB
both low, the 3-state B output
buffers are active and display the data present at the outputs of the
A latches
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; T
r
= T
f
≤
2.5ns
SYMBOL
t
PHL
/t
PLH
C
I
C
I/O
C
PD
PARAMETER
Propagation delay
A
n
to B
n
input capacitance
input/output capacitance
power dissipation capacitance per latch
V
CC
= 3.3 V
CONDITIONS
C
L
= 50 pF
V
CC
= 3.3 V
TYPICAL
3.3
5.0
10.0
27
UNIT
ns
pF
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
x V
CC2
x f
i
+Σ (C
L
x V
CC2
x f
o )
where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
x V
CC2
x f
o )
= sum of the outputs
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
24-Pin Plastic Small Outline (SO)
24-Pin Plastic Shrink Small Outline (SSOP) Type II
24-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH
AMERICA
74LVC543A D
74LVC543A DB
74LVC543A PW
NORTH AMERICA
74LVC543A D
74LVC543A DB
7LVC543APW DH
PKG DWG. #
SOT137-1
SOT340-1
SOT355-1
2000 Jun 21
2
853-1992 23942
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
74LVC543A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
CC
V
I
V
I/O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC Input voltage range
DC Output voltage range; output HIGH or LOW
state
DC input voltage range; output 3-State
Operating ambient temperature range in free-air
Input rise and fall times
V
CC
= 1.2 to 2.7 V
V
CC
= 2.7 to 3.6 V
CONDITIONS
MIN
2.7
1.2
0
0
0
–40
0
0
MAX
3.6
3.6
5.5
V
CC
5.5
+85
20
10
V
V
V
V
V
°C
ns/V
UNIT
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
I/O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage; output HIGH or LOW state
DC input voltage; output 3-State
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
t0
Note 2
V
O
uV
CC
or V
O
t
0
Note 2
Note 2
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +6.5
"50
–0.5 to V
CC
+0.5
–0.5 to 6.5
"50
"100
–65 to +150
500
500
UNIT
V
mA
V
mA
V
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2000 Jun 21
5
PCB Design
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