Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
PHP20NQ20T, PHB20NQ20T
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 200 V
I
D
= 20 A
g
R
DS(ON)
≤
130 mΩ
s
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. The device
has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.
The PHP20NQ20T is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB20NQ20T is supplied in the SOT404 (D
2
PAK) surface mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
drain
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404 (D
2
PAK)
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C; V
GS
= 10 V
T
mb
= 100 ˚C; V
GS
= 10 V
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
200
200
±
20
20
14
80
150
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin:2 of the SOT404 package
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
PHP20NQ20T, PHB20NQ20T
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
Non-repetitive avalanche
current
CONDITIONS
Unclamped inductive load, I
AS
= 19 A;
t
p
= 100
µs;
T
j
prior to avalanche = 25˚C;
V
DD
≤
25 V; R
GS
= 50
Ω;
V
GS
= 10 V; refer
to fig;15
MIN.
-
MAX.
252
UNIT
mJ
I
AS
-
20
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
SOT78 pckage, in free air
SOT404 package, pcb mounted, minimum
footprint
-
-
TYP. MAX. UNIT
-
60
50
1
-
-
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
Drain-source on-state
V
GS
= 10 V; I
D
= 10 A
resistance
Gate source leakage current V
GS
=
±10
V; V
DS
= 0 V
Zero gate voltage drain
V
DS
= 200 V; V
GS
= 0 V;
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
T
j
= 175˚C
T
j
= 175˚C
MIN.
200
178
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
3
-
-
120
-
0.02
0.05
-
65
10
22
15
46
50
38
3.5
4.5
7.5
2470
207
90
-
-
4
-
6
130
377
100
10
500
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
mΩ
mΩ
nA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
I
D
= 20 A; V
DD
= 160 V; V
GS
= 10 V
V
DD
= 100 V; R
D
= 4.7
Ω;
V
GS
= 10 V; R
G
= 5.6
Ω
Resistive load
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
PHP20NQ20T, PHB20NQ20T
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 20 A; V
GS
= 0 V
I
F
= 20 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 25 V
-
-
-
TYP. MAX. UNIT
-
-
0.95
124
0.74
20
80
1.2
-
-
A
A
V
ns
µC
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
PHP20NQ20T, PHB20NQ20T
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
10
Transient thermal impedance, Zth j-mb (K/W)
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
D
tp
D = tp/T
0.01
single pulse
T
0.001
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Drain Current, ID (A)
Tj = 25 C
18
16
14
12
10
8
6
4
2
4.8 V
4.6 V
4.4 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
5V
5.2 V
8V
VGS = 10V
6V
5.4 V
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
20
0
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); V
GS
≥
10 V
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
tp = 10 us
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
)
100
0.3
0.25
Drain-Source On Resistance, RDS(on) (Ohms)
4.4 V 4.6 V 4.8 V
5V
Tj = 25 C
10
D.C.
100 us
0.2
5.2 V
1 ms
0.15
10 ms
5.4 V
6V
8V
VGS = 10V
1
100 ms
0.1
0.05
0.1
1
10
100
Drain-Source Voltage, VDS (V)
1000
0
0
2
4
6
8
10
12
Drain Current, ID (A)
14
16
18
20
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
)
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
PHP20NQ20T, PHB20NQ20T
Drain current, ID (A)
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
Gate-source voltage, VGS (V)
175 C
Tj = 25 C
VDS > ID X RDS(ON)
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Threshold Voltage, VGS(TO) (V)
maximum
typical
minimum
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Transconductance, gfs (S)
VDS > ID X RDS(ON)
25
20
15
Tj = 25 C
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Drain current, ID (A)
30
1.0E-01
1.0E-02
175 C
1.0E-03
minimum
typical
1.0E-04
10
5
0
0
2
4
6
8
10
12
14
Drain current, ID (A)
16
18
20
maximum
1.0E-05
1.0E-06
0
0.5
1
1.5
2
2.5
3
3.5
Gate-source voltage, VGS (V)
4
4.5
5
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
)
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
10000
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C
Capacitances, Ciss, Coss, Crss (pF)
Ciss
1000
Coss
100
Crss
10
0.1
1
10
Drain-Source Voltage, VDS (V)
100
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
August 1999
5
Rev 1.000
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