PCA9632
4-bit Fm+ I
2
C-bus low power LED driver
Rev. 01 — 28 September 2007
Objective data sheet
1. General description
The PCA9632 is an I
2
C-bus controlled 4-bit LED driver optimized for
Red/Green/Blue/Amber (RGBA) color mixing applications. The PCA9632 is a drop-in
upgrade for the PCA9633 with 40× power reduction. In individual brightness control mode,
each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM
controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to
99.6 % to allow the LED to be set to a specific brightness value. In group dimming mode,
each LED output has its own 6-bit resolution (64 steps) fixed frequency Individual PWM
controller that operates at 6.25 kHz with a duty cycle that is adjustable from 0 % to 98.4 %
to allow the LED to be set to a specific brightness value. A fifth 4-bit resolution (16 steps)
Group PWM controller has a fixed frequency of 190 Hz that is used to dim all the LEDs
with the same value.
While operating in the Blink mode, each LED output has its own 8-bit resolution
(256 steps) fixed frequency individual PWM controller that operates at 1.5625 kHz with a
duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific
brightness value. Blink rate is controlled by the Group Frequency setting that has 8-bit
resolution (256 steps). The blink rate is adjustable between 24 Hz to once every
10.73 seconds. For Group Frequency settings between 6 Hz and 24 Hz, the Group PWM
has a 6-bit resolution (64 steps) with a duty cycle that is adjustable from 0 % to 98.4 %.
For Group frequency settings between 6 Hz to 0.09 Hz (once in 10.73 seconds), the
Group PWM has an 8-bit resolution (256 steps) with a duty cycle that is adjustable from
0 % to 99.6 %.
Each LED output can be off, on (no PWM control), set at its Individual PWM controller
value or at both Individual and Group PWM controller values. The LED output driver is
programmed to be either open-drain with a 25 mA current sink capability at 5 V or
totem-pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9632 operates with
a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be
directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external
drivers and a minimum amount of discrete components for larger current or higher voltage
LEDs.
The PCA9632 is in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher
frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF).
Software programmable LED Group and three Sub Call I
2
C addresses allow all or defined
groups of PCA9632 devices to respond to a common I
2
C-bus address, allowing for
example, all red LEDs to be turned on or off at the same time or marquee chasing effect,
thus minimizing I
2
C-bus commands.
NXP Semiconductors
PCA9632
4-bit Fm+ I
2
C-bus low power LED driver
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9632
through the I
2
C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set high-impedance. This allows an easy and
quick way to reconfigure all device registers to the same condition.
2. Features
I
40× power reduction compared to PCA9633
I
4 LED drivers. Each output programmable at:
N
Off
N
On
N
Programmable LED brightness
N
Programmable group dimming/blinking mixed with individual LED brightness
I
1 MHz Fast-mode Plus I
2
C-bus interface with 30 mA high drive capability on SDA
output for driving high capacitive buses
I
256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 1.5625 kHz PWM signal in individual
brightness mode
I
64-step (6-bit) linear programmable brightness for each LED output varying from fully
off (default) to maximum brightness using a 6.25 kHz PWM signal in Group dim mode
I
In group dim mode 16-step group brightness control allows global dimming (using a
190 Hz PWM signal) from fully off to maximum brightness (default)
I
256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 1.5625 kHz PWM signal in group blink mode
I
64-step group blinking with frequency programmable from 24 Hz to 6 Hz and
duty cycle from 0 % to 98.4 %
I
256-step group blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s)
and duty cycle from 0 % to 99.6 %
I
Four totem-pole outputs (sink 25 mA and source 10 mA at 5 V) with software
programmable open-drain LED outputs selection (default at high-impedance). No input
function.
I
Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
I
Software Reset feature (SWRST Call) allows the device to be reset through the
I
2
C-bus
I
400 kHz internal oscillator requires no external components
I
Internal power-on reset
I
Noise filter on SDA/SCL inputs
I
Edge rate control on outputs
I
No glitch on power-up
I
Supports hot insertion
I
Low standby current of < 1
µA
I
Operating power supply voltage range of 2.3 V to 5.5 V
I
5.5 V tolerant inputs
I
−40 °C
to +85
°C
operation
I
ESD protection exceeds 5000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
PCA9632_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 28 September 2007
2 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I
2
C-bus low power LED driver
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: TSSOP8, HVSON8
3. Applications
I
I
I
I
I
RGB or RGBA LED drivers for color mixing
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
4. Ordering information
Table 1.
Ordering information
Topside
mark
9632
9632
Package
Name
TSSOP8
HVSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm
plastic thermal enhanced very thin small outline package;
no leads; 8 terminals; body 3
×
3
×
0.85 mm
Version
SOT505-1
SOT908-1
Type number
PCA9632DP1
PCA9632TK
5. Block diagram
PCA9632
SCL
SDA
I
2
C-BUS
CONTROL
V
DD
V
SS
POWER-ON
RESET
LED
STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
24 Hz
to
0.09 Hz
GRPPWM
REGISTER
'0' – permanently OFF
'1' – permanently ON
002aad039
INPUT FILTER
V
DD
LEDn
6.25 kHz/
1.56 kHz
400 kHz
OSCILLATOR
GRPFREQ
REGISTER
MUX/
CONTROL
190 Hz
Fig 1. Block diagram of PCA9632
PCA9632_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 28 September 2007
3 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I
2
C-bus low power LED driver
6. Pinning information
6.1 Pinning
terminal 1
index area
LED0
LED1
LED0
LED1
LED2
LED3
1
2
3
4
002aad040
1
2
8
7
V
DD
SDA
SCL
V
SS
PCA9632TK
8
7
V
DD
SDA
SCL
V
SS
LED3
4
5
LED2
3
6
PCA9632DP1
6
5
002aad041
Transparent top view
Fig 2. Pin configuration for TSSOP8
Fig 3. Pin configuration for HVSON8
6.2 Pin description
Table 2.
Symbol
LED0
LED1
LED2
LED3
V
SS
SCL
SDA
V
DD
[1]
Pin description
Pin
1
2
3
4
5
[1]
6
7
8
Type
O
O
O
O
power supply
I
I/O
power supply
Description
LED driver 0
LED driver 1
LED driver 2
LED driver 3
supply ground
serial clock line
serial data line
supply voltage
HVSON package die supply ground is connected to both the V
SS
pin and the exposed center pad. The V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9632_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 28 September 2007
4 of 32
NXP Semiconductors
PCA9632
4-bit Fm+ I
2
C-bus low power LED driver
7. Functional description
Refer to
Figure 1 “Block diagram of PCA9632”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
7.1.1 Regular I
2
C-bus slave address
The I
2
C-bus slave address of the PCA9632 is shown in
Figure 4.
slave address
1
1
0
0
fixed
0
1
0
R/W
002aab318
Fig 4. Slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I
2
C-bus address
•
Default power-up value (ALLCALLADR register): E0h or 1110 000
•
Programmable through I
2
C-bus (volatile programming)
•
At power-up, LED All Call I
2
C-bus address is enabled. PCA9632 sends an ACK when
E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.
See
Section 7.3.8 “LED All Call I
2
C-bus address, ALLCALLADR”
for more detail.
Remark:
The default LED All Call I
2
C-bus address (E0h or 1110 000) must not be used
as a regular I
2
C-bus slave address since this address is enabled at power-up. All the
PCA9632s on the I
2
C-bus will acknowledge the address if sent by the I
2
C-bus master.
7.1.3 LED Sub Call I
2
C-bus addresses
•
3 different I
2
C-bus addresses can be used
•
Default power-up values:
–
SUBADR1 register: E2h or 1110 001
–
SUBADR2 register: E4h or 1110 010
–
SUBADR3 register: E8h or 1110 100
•
Programmable through I
2
C-bus (volatile programming)
•
At power-up, Sub Call I
2
C-bus addresses are disabled. PCA9632 does not send an
ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or
E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.
See
Section 7.3.7 “I
2
C-bus subaddress 1 to 3, SUBADRx”
for more detail.
PCA9632_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 28 September 2007
5 of 32
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