V59C1512(404/804/164)QC
HIGH PERFORMANCE 512 Mbit DDR2 SDRAM
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 8Mbit X 16 (164)
5
DDR2-400
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK4
)
Clock Cycle Time (t
CK5
)
Clock Cycle Time (t
CK6
)
System Frequency (f
CK max
)
5ns
5ns
5ns
5ns
200 MHz
37
DDR2-533
5ns
3.75ns
3.75ns
3.75ns
266 MHz
3
DDR2-667
5ns
3.75ns
3ns
3ns
333 MHz
25A
DDR2-800
5ns
3.75ns
3ns
2.5ns
400 MHz
25
DDR2-800
5ns
3.75ns
2.5ns
2.5ns
400 MHz
Features
■
High speed data transfer rates with system frequency
up to 400MHz
■
Posted CAS
■
Programmable CAS Latency: 3, 4, 5 and 6
■
Programmable Additive Latency:0, 1, 2, 3, 4 and 5
■
Write Latency=Read Latency-1
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 7.8 us (8192 cycles/64 ms)
■
OCD (Off-Chip Driver Impendance Adjustment)
■
ODT (On-Die Termination)
■
Weak Strength Data-Output Driver Option
■
Bidirectional differential Data Strobe (Single-ended
data-strobe is an optional feature)
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
JEDEC Power Supply 1.8V ± 0.1V
■
VDDQ=1.8V ± 0.1V
■
Available in 60-ball FBGA for x4 and x8 component or
84 ball FBGA for x16 component
■
PASR Partial Array Self Refresh
■
All inputs & outputs are compatible with SSTL_18 in-
terface
■
tRAS lockout supported
■
Read Data Strobe supported (x8 only)
■
Internal four bank operations with single pulsed RAS
Description
The V59C1512(404/804/164)QC is a four bank DDR
DRAM organized as 4 banks x 32Mbit x 4 (404), 4 banks x
16Mbit x 8 (804), or 4 banks x 8Mbit x 16 (164). The
V59C1512(404/804/164)QC achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
The chip is designed to comply with the following key
DDR2 SDRAM features:(1) posted CAS with additive la-
tency, (2)write latency=read latency-1, (3)Off-chip Driv-
er(OCD) impedance adjustment, (4) On Die Termination.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
s are synchronized with a pair of bidirectional strobes
(DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Available Speed Grade:
-5 (DDR2-400) @ CL 3-3-3
-37 (DDR2-533) @ CL 4-4-4
-3 (DDR2-667) @ CL 5-5-5
-25A (DDR2-800) @ CL 6-6-6
-25 (DDR2-800) @ CL 5-5-5
Device Usage Chart
Operating
Temperature
Range
0°C to 85°C
Package Outline
60 ball FBGA
84 ball FBGA
•
CK Cycle Time (ns)
-5
•
Power
-25
•
-37
•
-3
•
-25A
•
Std.
•
L
•
Temperature
Mark
Blank
V59C1512(404/804/164)QC Rev.1.1 April 2008
1
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QC
x4 pack age pinout (Top View) : 60ball FBGA Package
1
VDD
NC
2
NC
VSSQ
3
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
8
DQS
VSSQ
DQ0
VSSQ
9
VDDQ
NC
VDDQ
NC
VDD
ODT
VDDQ DQ1
NC
VSSQ
VDDL VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
VSSDL CK
RAS
CAS
A2
A6
A11
NC
CK
CS
A0
A4
A8
A13
VDD
VSS
Notes:
B1, B9, D1, D9 = NC for x4 organization.
Pins B3 has identical capacitance as pins B7.
VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device from
VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x4)
: Populated Ball
+
: Depopulated Ball
Top View (See the balls through the Package)
1
A
B
C
D
E
F
G
H
J
K
L
2
3
4
5
6
7
8
9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QC Rev. 1.1 April 2008
3
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QC
x8 package pinout (Top View) : 60ball FBGA Package
1
VDD
DQ6
VDDQ
DQ4
VDDL
2
NU/
RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
3
VSS
DM/
RDQS
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VSS
VDD
9
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x8)
: Populated Ball
+
: Depopulated Ball
Top View (See the balls through the Package)
1
A
B
C
D
E
F
G
H
J
K
L
2
3
4
5
6
7
8
9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QC Rev. 1.1 April 2008
4
Analogue and Mixed Signal
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