19-2173; Rev 1; 7/06
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
General Description
The MAX1183 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1183 is optimized for low-power, high
dynamic performance applications in imaging, instrumen-
tation, and digital communication applications. This ADC
operates from a single 2.7V to 3.6V supply, consuming
only 120mW while delivering a typical signal-to-noise ratio
(SNR) of 59.6dB at an input frequency of 20MHz and a
sampling rate of 40Msps. The T/H driven input stages
incorporate 400MHz (-3dB) input amplifiers. The convert-
ers may also be operated with single-ended inputs. In
addition to low operating power, the MAX1183 features a
2.8mA sleep mode as well as a 1µA power-down mode to
conserve power during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1183 features parallel, CMOS-compatible
three-state outputs. The digital output format can be set
to two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac-
ing. The MAX1183 is available in a 7mm
✕
7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible lower and higher speed versions of the
MAX1183 are also available. See Table 2 at end of data
sheet for a list of pin-compatible versions. Refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
and the MAX1184 data sheet for 20Msps. In addition to
these speed grades, this family includes a multiplexed
output version, for which digital data is presented time-
interleaved and on a single, parallel 10-bit output port.
Features
♦
Single 3V Operation
♦
Excellent Dynamic Performance:
59.6dB SNR at f
IN
= 20MHz
73dB SFDR at f
IN
= 20MHz
♦
Low Power:
40mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
♦
0.02dB Gain and 0.25° Phase Matching
♦
Wide ±1V
P-P
Differential Analog Input Voltage
Range
♦
400MHz -3dB Input Bandwidth
♦
On-Chip 2.048V Precision Bandgap Reference
♦
User-Selectable Output Format—Two’s
Complement or Offset Binary
♦
48-Pin TQFP Package with Exposed Paddle for
Improved Thermal Dissipation
MAX1183
Ordering Information
PART
MAX1183ECM
MAX1183ECM+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
48 TQFP-EP*
*EP
= Exposed paddle.
+Denotes
lead-free package.
Pin Configuration
REFOUT
D9A
45
44
REFP
REFIN
REFN
48
47
46
43
42
41
40
39
38
Applications
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
Video Application
Ultrasound
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
37
D8A
D7A
D6A
D5A
D4A
D3A
D2A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
MAX1183
EP
26
25
D1A
D0A
OGND
OV
DD
OV
DD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
V
DD
V
DD
GND
T/B
48 TQFP-EP
Functional Diagram appears at end of data sheet.
NOTE:
THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGE IS REPLACED BY A “+” SIGN.
________________________________________________________________
Maxim Integrated Products
SLEEP
PD
OE
D9B
D8B
D7B
D6B
GND
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
MAX1183
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND .............................................. -0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN,
COM, CLK to GND .................................-0.3V to (V
DD
+ 0.3V)
OE,
PD, SLEEP, T/B
D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP
(derate 30.4mW/°C above +70°C) ..........................2430mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Differential Input Voltage Range
Common-Mode Input Voltage
Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
Signal-to-Noise Ratio
(Note 3)
Signal-to-Noise and Distortion
(Note 3)
Spurious-Free Dynamic Range
(Note 3)
Total Harmonic Distortion
(First 4 harmonics) (Note 3)
Third-Harmonic Distortion
(Note 3)
Intermodulation Distortion
SNR
SINAD
SFDR
THD
HD3
f
INA or B
= 7.51MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 7.51MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 7.51MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 7.51MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 7.51MHz
f
INA or B
= 20MHz
f
INA or B
= 11.6066MHz at -6.5dBFS,
f
INA or B
= 13.3839MHz at -6.5dBFS
(Note 4)
57.3
56.8
57
56.5
65
65
59.6
59.6
59.4
59
76
73
-73
-73
-76
-73
-78
-64
-63
dB
dB
dBc
dBc
dB
f
CLK
40
5
MHz
Clock
Cycles
V
DIFF
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/2
±0.5
50
5
V
V
kΩ
pF
INL
DNL
f
IN
= 7.51MHz
f
IN
= 7.51MHz, no missing codes guaranteed
10
±0.5
±0.25
<±1
0
±1.7
±1.0
±1.8
±2
Bits
LSB
LSB
% FS
% FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IMD
dBc
2
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
REFIN Input Voltage
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Differential Reference Output
Voltage Range
REFIN Resistance
Maximum REFP, COM
Source Current
Maximum REFP, COM
Sink Current
Maximum REFN Source Current
Maximum REFN Sink Current
V
REFIN
V
REFP
V
REFN
∆V
REF
R
REFIN
I
SOURCE
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
∆V
REF
V
COM
V
REFP
V
REFN
Measured between REFP and COM and
REFN and COM
∆V
REF
= V
REFP
- V
REFN
∆V
REF
= V
REFP
- V
REFN
0.95
2.048
2.012
0.988
1.024
>50
5
-250
250
-5
1.10
V
V
V
V
MΩ
mA
µA
µA
mA
REFOUT
TC
REF
2.048
±3%
60
1.25
V
ppm/
°C
mV/mA
INA+ = INA- = INB+ = INB- = COM
FPBW
t
AD
t
AJ
For 1.5 x full-scale input
SYMBOL
CONDITIONS
Input at -20dBFS, differential inputs
Input at -0.5dBFS, differential inputs
MIN
TYP
500
400
1
2
2
±1
±0.25
0.2
MAX
UNITS
MHz
MHz
ns
ps
RMS
ns
%
Degrees
LSB
RMS
MAX1183
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
Differential Reference Input
Voltage Range
COM Input Voltage Range
REFP Input Voltage
REFN Input Voltage
4
1.024
±10%
V
DD
/2
±10%
V
COM
+
∆V
REF
/2
V
COM
-
∆V
REF
/2
kΩ
V
V
V
V
_______________________________________________________________________________________
3
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
MAX1183
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
0.8 x
V
DD
0.8 x
OV
DD
0.2 x
V
DD
0.2 x
OV
DD
0.1
V
IH
= OV
DD
or V
DD
(CLK)
V
IL
= 0V
5
I
SINK
= -200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
- 0.2
±10
0.2
±5
±5
TYP
MAX
UNITS
DIGITAL INPUTS (CLK, PD,
OE,
SLEEP, T/B)
CLK
Input High Threshold
V
IH
PD,
OE,
SLEEP, T/B
CLK
Input Low Threshold
V
IL
PD,
OE,
SLEEP, T/B
Input Hysteresis
Input Leakage
Input Capacitance
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Leakage
Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
V
DD
OV
DD
Operating, f
INA or B
= 20MHz at -0.5dBFS
I
VDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF,
f
INA or B
= 20MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA or B
= 20MHz at -0.5dBFS
Power Dissipation
PDISS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
t
DO
t
ENABLE
t
DISABLE
Figure 3 (Note 5)
Figure 4
Figure 4
5
10
1.5
8
ns
ns
ns
PSRR
Offset
Gain
2.7
1.7
3
2.5
40
2.8
1
5.8
100
2
120
8.4
3
±0.2
±0.1
45
10
180
15
3.6
3.6
60
V
V
mA
µA
mA
µA
mW
µW
mV/V
%V
V
HYST
I
IH
I
IL
C
IN
V
OL
V
OH
I
LEAK
C
OUT
V
V
V
µA
pF
V
V
µA
pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output Supply Current
I
OVDD
4
_______________________________________________________________________________________
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
SYMBOL
t
CH
t
CL
t
WAKE
CONDITIONS
Figure 3, clock period: 25ns
Figure 3, clock period: 25ns
Wake up from sleep mode (Note 6)
Wake up from shutdown (Note 6)
f
INA or B
= 20MHz at -0.5dBFS
f
INA or B
= 20MHz at -0.5dBFS
f
INA or B
= 20MHz at -0.5dBFS
MIN
TYP
12.5
±3.8
12.5
±3.8
0.41
1.5
-70
0.02
0.25
±0.2
MAX
UNITS
ns
ns
µs
MAX1183
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
dB
dB
Degrees
Note 1:
Equivalent dynamic performance is obtainable over full OV
DD
range with reduced C
L
.
Note 2:
Specifications at
≥
+25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 4:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 5:
Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 6:
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Typical Operating Characteristics
(V
DD
= 3V, OV
DD
= 2.5V, V
REFIN
= 2.048V, differential input at -0.5dBFS, f
CLK
= 40.0006MHz, C
L
≈
10pF, T
A
= +25°C, unless
otherwise noted.)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1183 toc01
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1183 toc02
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
-10
-20
AMPLITUDE (dB)
-30
-40
-50
-60
-70
-80
-90
-100
HD3
HD2
f
CLK
= 40.0006MHz
f
INA
= 24.9662MHz
f
INB
= 19.888MHz
A
INA
= -0.552dBFS
CHA
MAX1183 toc03
0
-10
-20
AMPLITUDE (dB)
-30
-40
-50
-60
-70
-80
-90
-100
0
2
4
6
8
HD3
HD2
CHA
f
CLK
= 40.0006MHz
f
INA
= 7.5343MHz
f
INB
= 6.1475MHz
A
INA
= -0.498dBFS
0
-10
-20
AMPLITUDE (dB)
-30
-40
-50
-60
-70
-80
-90
-100
HD2
HD3
CHB
f
CLK
= 40.0006MHz
f
INB
= 6.1475MHz
f
INA
= 7.5343MHz
A
INB
= -0.534dBFS
0
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
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