Intel® 6300ESB I/O Controller Hub
Datasheet
November 2007
Notice:
The Intel
®
6300ESB I/O Controller Hub may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Order Number: 300641-004US
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use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel
®
6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published
specifications.which may cause the product to deviate from published specifications. which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright © 2007, Intel Corporation. All rights reserved.
Intel
®
6300ESB I/O Controller Hub
DS
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November 2007
Order Number: 300641-004US
—Intel
®
6300ESB ICH
Intel
®
6300ESB I/O Controller Hub
Product Features
•
8-Bit Hub Interface
— 266 Mbyte/s maximum throughput
— Parallel Termination scheme for longer
trace lengths
— Supports Lower Voltages as per Hub
Interface 1.5 spec
PCI-X Bus I/F
— Supports PCI-X Rev 1.0 Specification at
66 MHz
— Supports PCI Rev 2.2 Specification at 33
MHz
— Support external master devices on PCI
— 4 @ PCI 33 MHz
— 2 @ PCI 64/66 MHz
— 4 @ PCI-X 64/66 MHz (two slots and
two soldered down devices)
— Support for 64-bit addressing on PCI-X
using DAC protocol
PCI Bus I/F
— Supports PCI 32b/33 MHz
— 120 Mbyte/s throughput
— Supports PCI Rev 2.2 Specification at 33
MHz
— Supports 4 external master devices @
33 MHz
— Support for 44-bit addressing on PCI
using DAC protocol.
— 4 slots supported
Integrated IDE Controller
— Supports “Native Mode” Register and
Interrupts
— Supports faster PIO timings for non-
data cycles
— Independent timing of up to four drives,
with separate Primary and Secondary
IDE cable connections
— Supports Ultra 100 DMA Mode Transfers
up to 100 Mbytes/s for reads from disk;
88.88 Mbytes/s for writes to disk, as
well as Ultra66 and Ultra33 DMA modes.
— PIO Mode four transfers up to 14
Mbytes/s
Integrated Serial ATA Host Controllers
— Independent DMA operation on two
ports
— Data transfer rates up to 150 Mbyte/s
— Alternate Device ID and RAID Class
Code option for support of Soft RAID
—
•
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Power Management Logic
— ACPI 1.0 compliant
— ACPI-defined power states S1 (Stop
Grant), S3 (STR), S4 (STD), S5 (SOFF)
— ACPI Power Management Timer
— SMI# Generation
— PCI PME#
— Supports THRMTRIP# input,
SYS_RESER# input and SLP_S4#
output
— Support for APM-based legacy power
management for non-ACPI
implementations
External Glue Integration
— Integrated Pull-up, Pull-down and Series
Termination resistors on IDE, CPU I/F
— Integrated Pull-down and Series
resistors on USB
Enhanced Hub I/F buffers improve routing
flexibility (Not available with all Memory
Controller Hubs)
Firmware Hub (FWH) I/F supports BIOS
Memory size up to 8 Mbytes
Low Pin Count (LPC) I/F
— New: No ISA/X-Bus support
— Allows connections of devices such as
Super I/O, microcontrollers, customers
ASICs
— Supports two Master/DMA devices
— Memory size up to 8 Mbytes
Enhanced DMA Controller
— Two cascaded 8237 DMA controllers
— Supports LPC DMA
— Supports DMA Collection Buffer to
provide
Type-F DMA performance for all DMA
channels
Real-Time Clock
— 256-byte battery-backed CMOS RAM
System TCO Reduction Circuits
— Timers to generate SMI# and Reset
upon detection of system hang
— Interrupt capability to OS-specific
manageability extension and OS
capability to call TCO BIOS Timers to
detect improper CPU reset
— Alert On Lan (AOL) to enable heartbeats
and system event reporting via LAN
controller
— Supports CPU BIST
— Supports ability to disable external
devices
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November 2007
Order Number: 300641-004US
Intel
®
6300ESB I/O Controller Hub
DS
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Intel
®
6300ESB ICH—
•
•
•
USB
— Includes one EHCI USB2 host
controllers, a total of four ports (shared
with the UHCI ports)
— Two UHCI Host Controllers for a total of
four ports (shared with EHCI ports)
— New: supports a USB 2.0 High-speed
Debug Port
— Supports wake-up from sleeping states
S1-S4
— Supports legacy Keyboard/Mouse
software with USB-based keyboard and
mouse
AC'97 Link for Audio and Telephony
CODECs
— New: Third AC_SDATA_IN Line for three
codec support
— AC’97 2.2 compliant
— New: Independent bus master logic for
8 channels (PCM In/Out, Mic 1 Input,
Mic 2 Input, Modem In/Out, S/PDIF
Out)
— Separate independent PCI functions for
Audio and Modem
— Support for up four to six channels of
PCM audio output (full AC3 decode)
— Support for 20-bit sample
— Support for ACPI device states - D0 and
D3
Interrupt Controller
— Supports up to 12 PCI interrupt pins;
four are not shared
— Two cascaded 82C59 with 15 interrupts
— Supports PCI scheme for delivering
interrupts as write cycles (MSI)
— Integrated I/O APIC capability with 24
interrupts
— Supports Serial Interrupt Protocol
— Supports Front-Side Message Interrupt
Delivery
New: Multimedia Timers based on 82C54
— Includes three timer comparators
— System timer, Refresh request, Speaker
tone output
— One-shot and periodic interrupts
supported
New: Watchdog Timer
— Two-Stage Watchdog with independent
count values for each stage
— First stage generates an INT or SMI
— Second stage drives external pin active
until cleared by a system reset or power
cycle
— Configuration option for write-once
enabling (count values can still change)
— Configurable granularity from 1µs to 10
min
•
•
•
SMBus
— Flexible SMBus/SMLink architecture to
optimize for ASF and eliminate board
requirements of SMBus 2.0 compliance
— Supports SMBus 2.0 Specification
— Host interface allows CPU to
communicate via SMBus
— Slave interface allows an external
Microcontroller to access system
resources
— Compatible with most 2-wire
components that are also I
2
C
compatible
New: Integrated 16550 compatible UARTs
— Enable/disable per UARTs
— Serial interrupts
— Can disable when external SIO used
New: Port 60/64 Emulation
— Programmable interrupt generation on
writes
— Positive decode to Port 60/64 emulation
registers
GPIO
— Four GPOs capable of directly driving
LEDs
— Two GPOs maintain state during and
after reset
1.5 V operation with 3.3 V I/O. 5 V
tolerance on many buffers, including IDE.
Package 37.5 x 37.5 mm 689 BGA
Process P859.6
•
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Intel
®
6300ESB I/O Controller Hub
DS
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November 2007
Order Number: 300641-004US
—Intel
®
6300ESB ICH
System Block Diagrams
Figure 1.
Workstation/PC Model
CPU
Graphics
AGP
GBE
HL 1.5
Intel
®
875P MCH
Memory
1GB to 4 GB
Hublink 1.5
FWH / SIO
LPC
IDE
IDE
Hard Disk
Hard Disk /
CD-DVD
Hard Disk
GBE / SCSI
Legacy Peripherals
PCI-X
PCI
Intel
®
6300ESB
I/O
Controller
Hub
SATA
SATA
USB 2.0
SM Bus
GPIO
AC'97
Hard Disk
B2475-02
November 2007
Order Number: 300641-004US
Intel
®
6300ESB I/O Controller Hub
DS
5
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