82544EI datasheet, PDF - EEWORLD Datasheet

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82544EI: DescriptionGigabit Ethernet Controller; File Size328KB，52 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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82544EI Overview

Gigabit Ethernet Controller

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82544EI Gigabit Ethernet Controller

Networking Silicon

Datasheet

Product Features

■

Full IEEE 802.3ab compliant

— Auto-Negotiation of speed, duplex, and

flow control configuration

32/64-bit 33/66 MHz, PCI Rev 2.2

compliant host interface

Host interface compliant to the PCI-X

addendum, revision 1.0a, from 50 MHz to

133 MHz

Offers both hardware and software based

IEEE 802.3z Auto-Negotiation and Link

Setup for Ten-Bit Interface (TBI) mode

Internally implements IEEE 802.3 MII

management interface for monitoring and

control of the internal PHY

Offers an external link interface: TBI as

specified in IEEE 802.3z standard for 1000

Mb/s full duplex operation with 1.25 Gb/s

SERDES

Receive and transmit IP and TCP/UDP

checksum offloading capabilities

Automatic MDI crossover operation for

100BASE-TX and 10BASE-T modes

IEEE 802.1q VLAN support

Implements enhanced ACPI register set and

power down functionality supporting D0

and D3 states, Wake on LAN capability

with Power Management Event support

■

Provides adaptive Inter Frame Spacing

(IFS) capability, enabling collision

reduction in half duplex networks

Enables control of the transmission of

Pause packets through software or

hardware triggering

Provides indications of receive FIFO status

through programming interface

Provides six activity and link indication

outputs to directly drive LEDs

Provides external parallel interface for up

to 4 Mb of Flash or Boot EPROM for boot

agent capability

4-wire 64 x 16 serial EEPROM interface

for loading product configuration

information

Operating temperature: 0°C to 70° C

(ambient)

Targeted power dissipation is 2.5 W

maximum

Provides boundary scan through IEEE

1149.1 (JTAG) Test Access Port

Leaded and lead-free

416-pin Ball Grid

Array (BGA). Devices that are lead-free are

marked with a circled “e1” and have a

product code: NHXXXXX

a.This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.

The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazard-

ous Substances (RoHS) -banned materials, is available at:

ftp://download.intel.com/design/packtech/material_content_IC_Pack

In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device.

For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.

Revision 1.0

April 2005

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet

Contents

1.0

Overview ............................................................................................................................ 1

1.1

1.2

1.3

1.4

2.0

2.1

2.2

2.3

2.4

2.5

2.6

3.0

3.1

3.2

Scope .................................................................................................................... 1

Reference Documents...........................................................................................1

Product Codes....................................................................................................... 2

Block Diagram ....................................................................................................... 3

PCI/PCI-X Features............................................................................................... 5

PHY-Specific Features .......................................................................................... 5

Host Offloading Features ...................................................................................... 5

Additional Performance Features.......................................................................... 5

Additional Device Features ................................................................................... 6

Technology Features............................................................................................. 6

Signal Type Definitions.......................................................................................... 7

PCI/PCI-X Bus Interface........................................................................................ 7

3.2.1 PCI Address, Data and Control Signals ................................................... 8

3.2.2 Arbitration Signals ..................................................................................10

3.2.3 Interrupt Signal .......................................................................................10

3.2.4 System Signals.......................................................................................10

3.2.5 Error Reporting Signals ..........................................................................10

3.2.6 Power Management Signals ..................................................................11

3.2.7 Impedance Compensation Signals.........................................................11

Ten-Bit Interface (TBI) Signals ............................................................................11

EEPROM/FLASH Interface Signals ....................................................................13

Miscellaneous Signals.........................................................................................13

3.5.1 LED Signals............................................................................................13

3.5.2 Other Signals..........................................................................................13

PHY Signals ........................................................................................................15

3.6.1 Crystal Signals .......................................................................................15

3.6.2 Analog Signals .......................................................................................15

Test Interface Signals..........................................................................................16

Power Supply Connections .................................................................................16

3.8.1 Digital Supplies.......................................................................................16

3.8.2 Analog Supplies .....................................................................................16

3.8.3 Ground and No Connects.......................................................................16

Targeted Absolute Maximum Ratings ................................................................17

Recommended Operating Conditions ................................................................18

Targeted DC Specifications ................................................................................18

Targeted AC Characteristics ..............................................................................21

Targeted Timing Specifications ...........................................................................23

4.5.1 PCI/PCI-X Bus Interface.........................................................................23

4.5.2 Targeted Link Interface Timing...............................................................27

4.5.3 FLASH Interface.....................................................................................30

Additional Features of the 82544EI Gigabit Ethernet Controller ........................................ 5

Signal Descriptions............................................................................................................. 7

3.3

3.4

3.5

3.6

3.7

3.8

4.0

Targeted Electrical and Timing Specifications .................................................................17

4.1

4.2

4.3

4.4

4.5

Datasheet

iii

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet

4.5.4

5.0

5.1

5.2

5.3

5.4

EEPROM Interface................................................................................. 31

Package and Pinout Information ...................................................................................... 33

Device Identification ............................................................................................ 33

Mechanical Specifications................................................................................... 33

Targeted Thermal Specifications ........................................................................ 35

Targeted Ball Mapping Diagram ......................................................................... 36

Figures

82544EI Gigabit Ethernet Controller Block Diagram............................................. 3

AC Test Loads for General Output Pins.............................................................. 22

PCI/PCI-X Clock Timing...................................................................................... 23

PCI Bus Interface Output Timing Measurement Conditions ............................... 24

PCI Bus Interface Input Timing Measurement Conditions .................................. 25

TVAL (max) Rising Edge Test Load.................................................................... 26

TVAL (max) Falling Edge Test Load ................................................................... 26

TVAL (min) Test Load ......................................................................................... 26

TVAL Test Load (PCI 5V Signalling Environment).............................................. 27

Output Slew Rate Test Load (PCI-X only) .......................................................... 27

Link Interface Rise/Fall Timing............................................................................ 28

Transmit Interface Timing ................................................................................... 28

Receive Interface Timing .................................................................................... 29

Flash Read Timing .............................................................................................. 30

Flash Write Timing .............................................................................................. 30

Device Identification: ........................................................................................... 33

Tables

Product Ordering Codes ....................................................................................... 2

Absolute Maximum Ratings (Referenced to VSS [Ground]) ............................... 17

Recommended Operating Conditions ................................................................. 18

DC Specifications................................................................................................ 18

Power Supply Characteristics – 1 ....................................................................... 18

Power Supply Characteristics – 2 ....................................................................... 19

AC Characteristics: 3.3 V Interfacing .................................................................. 21

Switching Current................................................................................................ 21

25Mhz Clock Input Requirements ....................................................................... 21

Link Interface Clock Requirements ..................................................................... 21

EEPROM Interface Clock Requirements ............................................................ 21

AC Test Loads for General Output Pins.............................................................. 22

PCI/PCI-X Bus Interface Clock Parameters........................................................ 23

PCI/PCI-X BUS Interface Timing Parameters, , ................................................. 24

PCI/PCI-X Bus Interface Timing Measurement Conditions................................. 25

Rise and Fall Time Definition .............................................................................. 27

Transmit Interface Timing ................................................................................... 28

Receive Interface Receive Timing ...................................................................... 29

Targeted Flash Read Operation Timing.............................................................. 30

Targeted Flash Write Operation Timing .............................................................. 31

EEPROM Interface Clock Timing........................................................................ 31

EEPROM Interface Clock Data Timing ............................................................... 31

82544GC Gigabit Ethernet Controller Thermal Characteristics .......................... 35

Datasheet

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet

1.0

Overview

The 82544EI Gigabit Ethernet Controller is an integrated third-generation Ethernet LAN

component capable of providing 1000, 100, and 10 Mbps data rates. It is a single-chip device,

containing both the MAC and PHY layer functions, and optimized for LAN on Motherboard

(LOM) designs, enterprise networking, and Internet appliances that use the Peripheral Component

Interconnect (PCI) and PCI-X bus backplanes.

The 82544EI utilizes a 32/64 bit, 33/66 MHz direct interface to the PCI bus, compliant with the

PCI Local Bus Specification, Revision 2.2. It also supports the emerging PCI-X extension to the

PCI Local Bus, Revision 1.0a. The controller interfaces with the host processor through on-chip

command and status registers and a shared host memory area, which is set up during initialization.

The 82544EI Gigabit Ethernet Controller provides a highly optimized architecture to deliver high

performance and PCI/PCI-X bus efficiency. Its hardware, acceleration features enable offloading

of various tasks, such as TCP/UDP/ IP checksum calculations and TCP segmentation, from the

host processor. The 82544EI device accommodates highly-configurable Ethernet designs, which

require minimal CPU overhead from interrupts and register accesses.

The physical layer circuitry provides an IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX and 10BASE-T applications. With the addition of an appropriate serializer/

deserializer (SERDES), the 82544EI controller also provides an Ethernet interface for 1000BASE-

SX or 1000BASE-LX applications.

The 82544EI Gigabit Ethernet Controller is packaged in a 27 mm x 27 mm, 416-ball grid array.

1.1

Scope

This document contains datasheet specifications for the 82544EI Gigabit Ethernet Controller

including signal descriptions, DC and AC parameters, packaging data, and pinout information.

1.2

Reference Documents

This document assumes that the designer is acquainted with high-speed design and board layout

techniques. The following documents provide additional information:

•

8254x Family of Gigabit Ethernet Controllers Software Developer’s Manual, Intel

Corporation.

•

PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group.

PCI-X Specification, Revision 1.0a, PCI Special Interest Group.

PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.

IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE).

IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE).

Datasheet

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