1:2 Fanout Buffer with Pre-Emphasis
854S712
Datasheet
Description
The 854S712 is a differential, high-speed 1:2 data/clock fanout buffer
and line driver. The outputs support pre-emphasis in order to drive
backplanes and long transmission lines while reducing inter-symbol
interference effects. The pre-emphasis level is configurable to
optimize for low bit error rate or power consumption. Pre-emphasis
utilizes an increased output voltage swing for transition bits.
The device is optimized for data rates up to 4.5 Gbps (NRZ) and for
deterministic jitter in data applications and low additive jitter in clock
applications. The outputs are LVDS-compliant while the differential
input is compatible with a variety of signal levels such as LVDS,
LVPECL and CML. Internal input termination, a bias voltage output
for AC-coupling and small packaging (VFQFN) supports
space-efficient board designs. The 854S712 operates from a 3.3V
power supply and supports the industrial temperature range of -40°C
to +85°C.
Features
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1:2 differential data/clock fanout buffer and line driver
4.5 Gbps data rate (NRZ) (maximum)
Differential LVDS outputs
Differential input supporting LVDS, LVPECL and CML levels
Configurable output pre-emphasis
Low-skew outputs: 10ps (maximum)
Low data deterministic jitter: 4ps (maximum)
LVCMOS interface levels for the control inputs
Asynchronous output disable into high-impedance state
Internal input termination: 100(Differential)
Additive phase jitter, RMS: 0.08ps (typical)
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
GND
PE0
PE1
V
DD
Block Diagram
nOE0
PE0
IN
V
TT
V
REF_AC
nIN
1
2
3
4
16
15
14
13
12
11
Q0
nQ0
Q1
nQ1
IN
Q0
nQ0
854S712
50
nIN
8XXXXXX
5
6
7
8
10
9
50
V
TT
Q1
nQ1
nOE0
nOE1
GND
nOE1
PE1
V
REF_A
VBB
16-pin, 3mm x 3mm VFQFN Package
V
DD
C
©2017 Integrated Device Technology, Inc.
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October 10, 2017
854S712 Datasheet
Pin Description and Pin Characteristic Tables
Table 1 Pin Description
Number
1
4
6, 7
15, 14
12, 11
10, 9
3
2
5, 16
8, 13
Name
IN
nIN
nOE0,
nOE1
PE0, PE1
Q0, nQ0
Q1, nQ1
V
REF_AC
V
TT
GND
V
DD
Power
Power
Input
Input
Input
Input
Output
Output
Output
Pulldown
Pulldown
Type
Description
Non-inverting differential data and clock input. LVDS, LVPECL or CML interface
levels. 50 to V
TT.
Inverting differential data and clock input. LVDS, LVPECL or CML interface levels.
50 to V
TT.
Output enable control. LVCMOS/LVTTL interface levels.
Pre-emphasis control. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Bias voltage reference for AC-coupling.
Center tap for input termination. Leave floating for LVDS input, connect to 50
to GND
for LVPECL inputs and to the V
REF_AC
output for AC-coupled applications.
Power supply ground.
Power supply pins.
NOTE:
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
2
51
Maximum
Units
pF
k
R
PULLDOWN
Input Pulldown Resistor
©2017 Integrated Device Technology, Inc.
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October 10, 2017
854S712 Datasheet
Device Configuration
Table 3A. Output Enable Control
Inputs
nOE1
0 (default)
0
1
1
nOE0
0 (default)
1
0
1
Q1, nQ1
Enabled
Enabled
Disabled (Logic 0)
Disabled (Logic 0)
Outputs
Q0, nQ0
Enabled
Disabled (Logic 0)
Enabled
Disabled (Logic 0)
NOTE: nOEx are asynchronous controls.
Table 3B. Output Pre-Emphasis Control
Input
PE1
0 (default)
0
1
1
PE0
0 (default)
1
0
1
Pre-Emphasis
Q1, nQ1
Off
Off
On
On
Q0, nQ0
Off
On
Off
On
NOTE: PEx are asynchronous controls.
©2017 Integrated Device Technology, Inc.
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October 10, 2017
854S712 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
I
IN,
Input Current, IN, nIN
V
TT,
Current, I
VT
V
REF_AC,
Input Sink/Source Current, I
REF_AC
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±50mA
±100mA
±2mA
74.7C (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
90
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
PE0, PE1,
nOE0, nOE1
PE0, PE1,
nOE0, nOE1
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
10
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
©2017 Integrated Device Technology, Inc.
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October 10, 2017
854S712 Datasheet
Table 4C. DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
REF_AC
I
IN
Parameter
Input Resistance
Input High Voltage
Input Low Voltage
IN, nIN
IN, nIN
IN, nIN
Test Conditions
IN to V
TT
Minimum
40
1.2
0
0.15
0.3
V
DD
- 1.35
IN, nIN
V
DD
- 1.30
Typical
50
Maximum
60
V
DD
V
IH
- 0.15
1.2
2.4
V
DD
- 1.25
35
Units
V
V
V
V
V
mA
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
Bias voltage reference
Input Current; NOTE 2
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram.
NOTE 2: Guaranteed by design.
Table 4D. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Pre-Emphasis off (PE0=PE1=0)
Pre-Emphasis off (PE0=PE1=0)
Pre-Emphasis off (PE0=PE1=0)
Pre-Emphasis off (PE0=PE1=0)
1.10
1.25
Minimum
300
Typical
450
Maximum
650
50
1.40
50
Units
mV
mV
V
mV
©2017 Integrated Device Technology, Inc.
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October 10, 2017
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