Technology Licensed from International Rectifier
APU3146
DUAL SYNCHRONOUS PWM CONTROLLER WITH
CURRENT SHARING CIRCUITRY AND AUTO-RESTART
FEATURES
Dual Synchronous Controller with 180 out-of-phase
Configurable to 2-Independent Outputs or 2-Phase
Single Output
Current Sharing Using Inductor's DCR
Current Limit using MOSFET's R
DS(ON)
Hiccup/Latched Current Limit
Latched Over-Voltage Protection
Vcc from 4.5V to 16V Input
Programmable Switching Frequency up to 500KHz
Two Independent Soft-Starts/ Shutdowns
0.8V Precision Reference Voltage Available
Power Good Output
External Frequency Synchronization
DESCRIPTION
The
APU3146
IC combines a Dual synchronous Buck
controller, providing a cost-effective, high performance
and flexible solution. The
APU3146
can configured as 2-
independent or as 2-phase controller. The 2-phase con-
figuration is ideal for high current applications. The
APU3146
features 180 out of phase operation which re-
duces the required input/output capacitance and results
to few number of capacitor quantity. Other key features
offered by this device include two independent program-
mable soft starts, programmable switching frequency up
to 500KHz per phase, under voltage lockout function.
The current limit is provided by sensing the lower
MOSFET's on-resistance for optimum cost and perfor-
mance.
2-Phase Power Suppl
y
Graphic Card
DDR Memory Applications
D1
C12
APPLICATIONS
Embedded Computer Systems
Telecom Systems
Point of Load Power Architectures
12V
C11
C3
C4
V
CL
VcH1
V
OUT3
VcH2
Vcc
HDrv1
C13
R1
C14
Q2
L3
C5
OCSet1
Hiccup
LDrv1
PGnd1
V
P2
Q3
R5
Sync
1.8V @ 30A
C15
R2
V
REF
Rt
C8
R3
U1
APU3146
V
SEN1
D2
BAT54A
R10
C16
R11
R7
Comp1
C9
V
SEN2
Fb1
Fb2
C17
R9
C18
L4
R8
R4
Comp2
HDrv2
OCSet2
R6
Q4
Q5
PGood
PGood
SS1 / SD
C10
SS2 / SD
LDrv2
PGnd2
Gnd
Figure 1 - Typical application of
APU3146
in 2-phase configuration with inductor current sensing
PACKAGE ORDER INFORMATION
DEVICE
APU3146O(/M)
Data and specifications subject to change without notice.
PACKAGE
28-Pin TSSOP(/SOIC
WB)
200407061-1/28
APU3146
ABSOLUTE MAXIMUM RATINGS
Vcc, V
CL
Supply Voltage .............................................. -0.5V To 16V
VcH1 and VcH2 Supply Voltage ................................ -0.5V To 25V
PGOOD................. ................................................... -0.5V To 16V
Storage Temperature Range ...................................... -40°C To 125°C
Operating Junction Temperature Range ..................... -40°C To 125°C
Caution:
Stresses above those listed in Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
28-PIN TSSOP (O)
PGood
1
V
CC
2
V
OUT3
3
Rt
4
V
SEN2
5
Fb2
6
Comp2
7
SS2 / SD
8
OCSet2
9
VcH2
10
HDrv2
11
PGnd2
12
LDrv2
13
V
CL
14
28
Gnd
27
V
REF
26
V
P2
25
Hiccup
24
Sync
23
V
SEN1
22
Fb1
21
Comp1
20
SS1 / SD
19
OCSet1
18
VcH1
17
HDrv1
16
PGnd1
15
LDrv1
28-PIN SOIC WIDE BODY(M)
PGood
1
V
CC
2
V
OUT3
3
Rt
4
V
SEN2
5
Fb2
6
Comp2
7
SS2 / SD
8
OCSet2
9
VcH2
10
HDrv2
11
PGnd2
12
LDrv2
13
V
CL
14
28
Gnd
27
V
REF
26
V
P2
25
Hiccup
24
Sync
23
V
SEN1
22
Fb1
21
Comp1
20
SS1 / SD
19
OCSet1
18
VcH1
17
HDrv1
16
PGnd1
15
LDrv1
Rth
JA
= 84°C/W
Rth
JA
=80
o
C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=12V, VcH1=VcH2=V
CL
=12V and T
A
=0 to 70°C.
Typical values refer to T
A
=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures
equal to the ambient temperature.
PARAMETER
Reference Voltage Section
Reference Voltage
Voltage Line Regulation
UVLO Section
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - VcH1
UVLO Hysteresis - VcH1
UVLO Threshold - VcH2
UVLO Hysteresis - VcH2
Supply Current Section
Vcc Dynamic Supply Current
VcH1 & VcH2 Dynamic Current
V
CL
Dynamic Supply Current
Vcc Static Supply Current
VcH1/VcH2 Static Current
V
CL
Static Supply Current
SYM
V
REF
L
REG
TEST CONDITION
MIN
0.789
5<Vcc<12
3.9
3.2
3.2
TYP
0.805
0.02
4.2
0.25
3.5
0.1
3.5
0.1
10
15
15
10
6
6
MAX
0.821
0.04
4.5
3.8
3.8
UNITS
V
%/V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
2/28
UVLO
V
CC
Supply Ramping Up
Ramp Up and Ramp Down
UVLO
V
C
H1
Supply Ramping Up
Ramp Up and Ramp Down
UVLO
V
C
H2
Supply Ramping Up
Ramp Up and Ramp Down
Dyn I
CC
Dyn I
CH
Dyn I
CL
I
CCQ
I
CHQ
I
CLQ
Freq=300KHz, C
L
=1500pF
Freq=300KHz, C
L
=1500pF
Freq=300KHz, C
L
=1500pF
SS=0V
SS=0V
SS=0V
15
25
25
15
10
10
APU3146
PARAMETER
Soft-Start Section
Charge Current
Power Good Section
V
SENS1
Lower Trip Point
V
SENS2
Lower Trip Point
PGood Output Low Voltage
Error Amp Section
Fb Voltage Input Bias Current
Transconductance 1
Transconductance 2
Error Amp Source/Sink Current
Input Offset Voltage for PWM1/2
VP2 Voltage Range
Oscillator Section
Frequency
Ramp Amplitude
Synch Frequency Range
Synch Pulse Duration
Synch High Level Threshold
Synch Low Level Threshold
V
OUT3
Internal Regulator
Output Voltage
Output Current
Protection Section
OVP Trip Threshold
OVP Fault Prop Delay
Current Limit Threshold
Current Source
Hiccup Duty Cycle
Hiccup High Level Threshold
Hiccup Low Level Threshold
Output Drivers Section
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
Min Pulse Width
Thermal Shutdown Trip Point
Thermal Shutdown Hysteresis
SYM
SS
IB
PG
FB1L
PG
FB2H
TEST CONDITION
SS=0V
V
SENS1
Ramping Down
V
SENS2
Ramping Down
I
SINK
=2mA
SS=3V
1400
1400
60
-5
0.8
MIN
20
TYP
25
MAX
32
UNITS
µA
V
V
V
µA
µmho
µmho
µA
mV
V
KHz
Freq
V
RAMP
Rt
(SET)
to 30K
Note1
20% above free running freq
Note1
Note1
255
1.25
800
200
2
300
0.8
5.9
50
OVP
OCSet
6.2
6.7
345
V
KHz
ns
V
V
V
mA
V
µs
µA
%
V
V
ns
ns
ns
%
%
ns
C
C
0.8
V
REF
0.9
V
REF
0.95
V
REF
0.8
V
REF
0.9
V
REF
0.95
V
REF
0.1
0.5
-0.1
-0.5
2300
2300
140
+5
1.5
I
FB1
g
m1
g
m2
V
OS(ERR)2
VP2
Fb to V
REF
Note1
100
0
1.1
V
REF
1.15
V
REF
1.2
V
REF
Output forced to 1.125V
REF,
Note1
5
16
20
24
Hiccup pin pulled high, Note1
5
Note1
2
0.8
C
L
=1500pF, Figure 2
C
L
=1500pF, Figure 2
Figure 2
Fb=0.6V, F
SW
=300KHz
Fb=1V
F
SW
=300KHz, Note1
Note 1
18
25
50
85
0
150
T
r
T
f
T
DB
D
MAX
D
MIN
Puls(min)
50
50
100
140
20
Note 1:
Guaranteed by design but not tested for production.
3/28
APU3146
DEADBAND TIME
Tr
90%
High Side
Driver HD 2V
10%
Tr
90%
Low Side
Driver LD 2V
10%
Deadband
H_to_L
Deadband
L_to_H
Tf
Tf
Figure 2 - Deadband time definition.
T
DB(TYP)
=(Deadband H_toL+Deadband L_to -H)/2
PIN DESCRIPTIONS
PIN#
1
2
3
4
5,23
6,22
PIN DESCRIPTION
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC.
Output of the internal LDO.
Switching frequency setting resistor. (see Figure 10 for selecting resistor values).
Sense pins for OVP and PGood. For 2-Phase operation tie these pins together.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
Comp2, Comp1 Compensation pins for the error amplifiers.
These pins provide soft-start for the switching regulator. An internal current source charges
SS2 / SD
external capacitors that are connected from these pins to ground which ramp up the
output of the switching regulators, preventing them from overshooting as well as limiting
SS1 / SD
the input current. The converter can be shutdown by pulling these pins below 0.3V.
OCSet2,OCSet1 Current limit resistor (R
LIM
) connection pins for output 1 and 2. The other ends of R
LIM
s are
connected to the corresponding switching nodes.
VcH2, VcH1 Supply voltage for the high side output drivers. These are connected to voltages that must
be typically 6V higher than their bus voltages. A 1µF high frequency capacitor must be
connected from these pins to GND to provide peak drive current capability.
HDrv2, HDrv1 Output drivers for the high side power MOSFETs.
1)
PGnd2, PGnd1 These pins serve as the separate grounds for MOSFET drivers and should be connected
to the system’s ground plane.
LDrv2, LDrv1 Output drivers for the synchronous power MOSFETs.
V
CL
Supply voltage for the low side output drivers. This pin should be high for normal operation
Sync
The internal oscillator may be synchronized to an external clock via this pin.
Hiccup
When pulled High, it puts the device current limit into a hiccup mode. When pulled Low,
the output latches off, after an overcurrent event.
4/28
PIN SYMBOL
PGood
Vcc
V
OUT3
Rt
V
SEN2
, V
SEN1
Fb2,Fb1
7,21
8
20
9,19
10,18
11,17
12,16
13,15
14
24
25
APU3146
PIN DESCRIPTIONS
PIN#
26
27
28
PIN SYMBOL
V
P2
V
REF
Gnd
PIN DESCRIPTION
Non-inverting input to the second error amplifier. In the current sharing mode, it is con-
nected to the programming resistor. In independent 2-channel mode it is connected to
V
REF
pin when Fb2 is connected to the resistor divider to set the output voltage.
Reference Voltage. The drive capability of this pin is about 2uA.
Analog ground for internal reference and control circuitry. Connect to PGnd plane with a
short trace.
1)
These pins should not go negative (-0.5V), this may cause instability for the gate drive circuits. To prevent this,
a low forward voltage drop diode is required between these pins and ground as shown in Figure 1.
BLOCK DIAGRAM
Vcc
2
25uA 25uA
SS2 / SD
SS1 / SD
POR
8
20
64uA
Max
64uA
Mode
Bias
Generator
4.2V / 4.0V
3V
0.8V
POR
V
P2
0.8V
Mode
Control
POR
Mode
18
VcH1
HDrv1
VcH1
VcH2
3.5V / 3.3V
3.5V / 3.3V
UVLO
17
0.3V
PWM Comp1
Error Amp1
0.8V
Thermal
Shutdown
SS1
14
15
V
CL
LDrv1
PGnd1
OCSet1
R
Q
Ramp1
Set1
Two Phase
Oscillator
Ramp2
3uA
SS1
16
Fb1
Comp1
Rt
Sync
V
REF
22
S
19
21
Reset Dom
Set2
Reset Dom
20uA
4
10
11
VcH2
HDrv2
Hiccup
24
S
0.8V
Error Amp2
PWM Comp2
27
Q
R
SS1
SS2
Mode
0.3V
Hiccup
Control
25
V
P2
26
13
12
LDrv2
PGnd2
OCSet2
Fb2
Comp2
V
SEN1
V
SEN2
Gnd
6
SS2
7
23
5
28
SS2
PGood / OVP
OVP
HDrv OFF / LDrv ON
9
3uA
20uA
1
PGood
V
OUT3
Regulator
3
Figure 3 - Block diagram of
APU3146.
5/28
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