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WS1M8-17CI

Description
Standard SRAM, 1MX8, 17ns, CMOS, CDIP32, SIDE BRAZED, CERAMIC, DIP-32
Categorystorage    storage   
File Size162KB,6 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

WS1M8-17CI Overview

Standard SRAM, 1MX8, 17ns, CMOS, CDIP32, SIDE BRAZED, CERAMIC, DIP-32

WS1M8-17CI Parametric

Parameter NameAttribute value
package instructionSIDE BRAZED, CERAMIC, DIP-32
Reach Compliance Codeunknown
Maximum access time17 ns
Other featuresTTL COMPATIBLE INPUTS/OUTPUTS
JESD-30 codeR-CDIP-T32
memory density8388608 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count1048576 words
character code1000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1MX8
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal locationDUAL
Base Number Matches1
WS1M8-XXX
HI-RELIABILITY PRODUCT
2x512Kx8 DUALITHIC™ SRAM
FEATURES
s
Access Times 17, 20, 25, 35, 45, 55ns
s
Revolutionary, Center Power/Ground Pinout
s
Packaging:
• 32 pin, Hermetic Ceramic DIP (Package 300)
• 36 lead Ceramic SOJ (Package 100)
• 36 lead Ceramic Flatpack (Package 226)
PIN CONFIGURATION FOR WS1M8-XDJX
AND WS1M8-XFX
36 CSOJ
36 FLATPACK
s
Organized as two banks of 512Kx8
s
Commercial, Industrial and Military Temperature Ranges
s
5 Volt Power Supply
s
Low Power CMOS
s
TTL Compatible Inputs and Outputs
PIN CONFIGURATION FOR WS1M8-XCX
32 DIP
TOP VIEW
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A14
A13
A12
A11
A10
CS2
TOP VIEW
A0
A1
A2
A3
A4
CS1
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
CS2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTION
A
0-18
I/O
0-7
CS
1-2
OE
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
PIN DESCRIPTION
A
0-18
I/O
0-7
CS
1-2
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Write Enable
+5.0V Power
Ground
BLOCK DIAGRAM
I/O
0-7
WE
OE
A
0-18
BLOCK DIAGRAM
I/O
0-7
WE
A
0-18
512K x 8
512K x 8
512K x 8
512K x 8
CS
1
(1)
CS
2
(1)
NOTE:
1. CS
1
and CS
2
are used to select the lower and upper 512Kx8 of the device. CS
1
and CS
2
must not be enabled at the same time.
CS
1
(1)
CS
2
(1)
October 2000 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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