W83195BR-341
W83195BG-341
WINBOND CLOCK GENERATOR
FOR VIA P4/KT SERIES CHIPSET
Date: Mar/21/2006
Revision: 1.1
W83195BR-341/W83195BG-341
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
W83195BR-341/W83195BG-341 Data Sheet Revision History
WEB
VERSION
PAGES
DATES
VERSION
MAIN CONTENTS
1
2
3
4
5
6
7
8
9
1
0
n.a.
n.a.
19
07/07/03
26/8/03
12/18/03
05/03/04
03/21/06
0.5
0.6
0.7
1.0
1.1
n.a.
n.a.
n.a.
1.0
1.1
All of the versions before 0.50 are for
internal use.
First published preliminary version.
Some description red text part
Correction IC version,
Update on web
Add lead-free part number W83195BG-341
Please note that all data and specifications are subject to change without notice. All
the trademarks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
-I-
Publication Release Date: March, 2006
Revision 1.1
W83195BR-341/W83195BG-341
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
Table of Content-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 1
PRODUCT FEATURES .............................................................................................................. 1
PIN CONFIGURATION ............................................................................................................... 2
BLOCK DIAGRAM ...................................................................................................................... 2
PIN DESCRIPTION..................................................................................................................... 3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.
7.
Crystal I/O.................................................................................................................................3
CPU, AGP, PCI Clock Outputs................................................................................................3
Fixed Frequency Outputs.........................................................................................................4
DRAM Buffer ............................................................................................................................5
I2C Control Interface ................................................................................................................5
Output Control Pins ..................................................................................................................5
Power an GND Pins .................................................................................................................6
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7
I2C CONTROL AND STATUS REGISTERS .............................................................................. 8
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
Register 0: Frequency Select (Default =08h) ..........................................................................8
Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h)...................................8
Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) .............................................9
Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)..................9
Register 4,5 Reserved .............................................................................................................9
Register 6: M/N Program (Default: 8Bh) .................................................................................9
Register 7: M/N Program (Default: 2Fh)................................................................................10
Register 8: Spread Spectrum Program (Default: 1Fh)..........................................................10
Register 9: Divider Ratio (Default: 03h).................................................................................10
Register 10: Control (Default: 0Ah)........................................................................................11
Register 11: Control (Default: E7h)........................................................................................12
Register 12: Control (Default: 3Ch) .......................................................................................12
Register 13: Control (Default: 24h) ........................................................................................13
Register 14: Control (Default: 56h) ........................................................................................13
Register 15: Slew Rate Control (Default: 55h) ......................................................................13
Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh).......................14
Register 17: Slew Rate Control (Default: CFh) .....................................................................14
Register 18: M/N Time & Type Control (Default: 5Bh)..........................................................14
Register 19: Reserved ...........................................................................................................15
Register 20: Winbond Chip ID – (Ready Only) (Default: 61h)..............................................15
Register 21: Winbond Chip ID – (Ready Only) (Default: 50h)..............................................15
- II -
W83195BR-341/W83195BG-341
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
8.
ACCESS INTERFACE .............................................................................................................. 16
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10.
11.
12.
Block Write protocol ...............................................................................................................16
Block Read protocol ...............................................................................................................16
Byte Write protocol .................................................................................................................16
Byte Read protocol.................................................................................................................16
ABSOLUTE MAXIMUM RATINGS .......................................................................................17
General Operating Characteristics ........................................................................................17
Skew Group timing clock........................................................................................................17
CPU 0.7V Electrical Characteristics ......................................................................................18
CPU 1.0V Electrical Characteristics ......................................................................................18
AGP Electrical Characteristics ...............................................................................................18
PCI Electrical Characteristics.................................................................................................19
24M, 48M Electrical Characteristics ......................................................................................19
REF Electrical Characteristics ...............................................................................................19
SPECIFICATIONS .................................................................................................................... 17
ORDERING INFORMATION..................................................................................................... 20
HOW TO READ THE TOP MARKING...................................................................................... 20
PACKAGE DRAWING AND DIMENSIONS.............................................................................. 21
- III -
Publication Release Date: March, 2006
Revision 1.1
W83195BR-341/W83195BG-341
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
1. GENERAL DESCRIPTION
The W83195BR-341 is a Clock Synthesizer for Intel P4 Springdale/Prescott series chipset and support
AMD Athlon processors. W83195BR-341 provides all clocks required for high-speed microprocessor
and provides step-less frequency programming and 32 different frequencies of CPU, AGP, and PCI
clocks setting. All clocks are externally selectable with smooth transitions.
The W83195BR-341 provides I
2
C serial bus interface to program the registers to enable or disable
each clock outputs and provides +/-0.25%, +/-0.5% center type and –0.5%, -1.0% down type spread
spectrum or programmable S.S.T. scale to reduce EMI.
The W83195BR-341 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
•
1 pairs differential clock for CPU (P4 or Athlon)
•
1 pairs differential clock for Chipset
•
3 AGP clock outputs
•
Support two DDR DIMMS or three SDRAM DIMMS
•
7 PCI synchronous clocks, 1 free running
•
1 48MHz clock outputs for USB
•
1 24_48MHz for I/O chip, default 24MHz
•
2 REF 14.318MHz clock outputs
•
AGP leads PCICLK from 1.5ns to 3.5ns
•
I
2
C 2-Wire serial interface supports block and byte mode read/write
•
Step-less frequency programming
•
Smooth frequency switch with selections from 66 to 200MHz
•
Programmable clock outputs Slew rate control and Skew control
•
+/- 0.25% center type spread spectrum in table mode
•
Programmable S.S.T. scale to reduce EMI
•
Programmable registers to enable/stop each output and select modes
•
56-pin SSOP package
-1-
Publication Release Date: March, 2006
Revision 1.1
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