UTC L8115
LINEAR INTEGRATED CIRCUIT
FET BIAS CONTROLLER WITH
POLARISATION SWITCH AND
TONE DETECTION
DESCRIPTION
The UTC L8115 is designed to meet the bias
requirements of GaAs and HEMT FETs commonly used in
satellite receiver LNBs, PMR, cellular telephones etc. with
a minimum of external components.
With the addition of two capacitors and a resistor the
devices provide drain voltage and current control for three
external grounded source FETs, generating the regulated
negative rail required for FET gate biasing whilst operating
from a single supply. This negative bias, at -2.8 volts, can
also be used to supply other external circuits.
The UTC L8115 includes bias circuits to drive up to three
external FETs. A control input to the device selects either
one of two FETs as operational, the third FET is
permanently active. This feature is normally used as an
LNB polarization switch. Also specific to Universal LNB
applications is the 22kHz tone detection and logic output
feature which is used to enable high and low band
frequency switching.
Drain current setting of the UTC L8115 is user selectable
over the range 0 to 15mA, this is achieved with addition of
a single resistor. The UTC L8115 gives 2.2 volts drain
whilst.
SSOP-16(150mil)
SSOP-20(150mil)
FEATURES
*Provides bias for GaAs and HEMT FETs.
*Drives up to three FETs.
*Dynamic FET protection.
*Drain current set by external resistor.
*Regulated negative rail generator requires only 2 external
capacitors.
*Choice in drain voltage
*Wide supply voltage range
*Polarisation switch for LNBs
*22KHz tone detection for band switching.
*Tone detector ignores unwanted signals
*Support fr MIMIC, FET and Bipolar local oscillator devices
APPLICATIONS
*Satellite receiver LNBs
*Private mobile radio(PMR)
*Cellular telephones
UTC
UNISONIC
TECHNOLOGIES
CO., LTD.
1
QW-R123-005,B
UTC L8115
PARAMETER
Filter Amplifier
Bias Voltage
5
Input Impedance
Amplifier Gain
V Threshold
5
Output Stage
Lov Volt.Range
6
Lov Bias Current
L
B
Output Low
V
LBL
L
B
Output High
H
B
Output Low
V
HBL
H
B
Output High
LINEAR INTEGRATED CIRCUIT
SYMBOL
V
OUT
Finz
AG
FV
T
V
Lov
I
LOV
TONE DETECTION CHARACTERISTICS
TEST CONDITONS
I
FIN
=0
V
FIN
=100mV p/p
V
FIN
=100mV p/p
100
I
L
=50mA(L
B
or H
B
)
V
LOV
=0
V
LOV
=0, I
L
=0
RIb-Csub=1MΩ
V
LOV
=3V, I
L
=0mA
RIb-Gnd=1MΩ
V
LOV
=0, I
L
=10mA
V
LOV
=3V ,I
L
=50mA
V
LOV
=0 ,I
L
=0
Rhb-Csub=1MΩ
V
LOV
=3V, I
L
=0mA
Rhb-Gnd=1MΩ
V
LOV
=0, I
L
=10mA
V
LOV
=3V, I
L
=50mA
Enabled
6
Enabled
6
MIN.
1.75
TYP.
1.95
150
30
170
MAX.
2.15
UNIT
V
Ω
V/mA
mVp/p
V
μA
V
V
V
V
V
V
350
Vcc-1.8
1.0
-2.55
0.1
0.025
3.1
-2.55
0.1
0.025
3.1
-0.5
0.02
-3.05
-0.01
-0.025
2.9
-3.05
-0.01
-0.025
2.9
0.15
-2.80
0
0
3.0
-2.80
0
0
3.0
V
LBH
Disabled
6
Disabled
6
Disabled
6
Disabled
6
Enabled
6
Enabled
6
V
HBH
POLARITY SWITCH CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITONS
V
POL
=25V (Applied via R
POL
=2kΩ)
MIN.
TYP.
MAX.
UNIT
μA
Input Current
I
POL
10
25
40
Threshold
V
TPOL
14
14.75
15.5
V
V
POL
=25V (Applied via R
POL
=2kΩ)
Voltage
V
POL
=25V (Applied via R
POL
=2kΩ)
Switching Speed
T
SPOL
100
ms
NOTES:
1.
The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors,
C
NB
and C
SUB
, of 47nF are required for this purpose.
2.
The characteristics are measured using an external reference resistor R
CAL
of value 33k wired from pins R
CAL
to ground.
3.
Noise voltage is not measured in production.
4.
Noise voltage measurement is made with FETs and gate and drain capacitors in place on all
outputs.C
G
,4.7nF,are connected between gate output and ground,C
D
,10nF,are connected between drain
outputs and ground.
5.
These parameters are linearly related to Vcc.
6.
These parameters are measured using Test Circuit 1
UTC
UNISONIC
TECHNOLOGIES
CO., LTD.
4
QW-R123-005,B
UTC L8115
TEST CIRCUIT 1
LINEAR INTEGRATED CIRCUIT
G1
V1
D1
5V DC G2
+
D2
-
G3
D3
Gnd
Cnb1
Cnb2
C
NB
N/C
47nF
UTC L8115
SSOP20(150mil)
1
Vcc
Rcal
Vpol
Fin
NC
NC
Lov
HB
LB
Csub
C
SUB
47nF
R
1
33k
C
F1
4.7nF
R2
2k
V2
See Note 1
+
-
Note 1: V2 Characteristics
Type: AC source
Frequency: 22kHz
Voltage: 350mVp/p Enabled
100mVp/p Disabled
Note:Same circuit used for SSOP16(150mil) but with adjusted pinout.
TYPCIAL CHARACTERISTICS
JFET Drain Curretn vs Rcal
16
14
Drain Current (mA)
12
Vsub (V)
10
8
6
4
2
0
0
20
40
60
Rcal (k)
80
100
Vcc=5V
Vsub vs External Load
Note: Operation with loads>200μA is not
guaranteed.
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
Vcc=5V
6V
8V
10V
0.2
0.4
0.6
0.8
1.0
External Vsub Load (mA)
UTC
UNISONIC
TECHNOLOGIES
CO., LTD.
5
QW-R123-005,B
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