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MC75172B, MC75174B
Quad EIA−485 Line Drivers
with Three−State Outputs
The ON Semiconductor MC75172B/174B Quad Line drivers are
differential high speed drivers designed to comply with the EIA−485
Standard. Features include three−state outputs, thermal shutdown, and
output current limiting in both directions. These devices also comply
with EIA−422−A, and CCITT Recommendations V.11 and X.27.
The MC75172B/174B are optimized for balanced multipoint bus
transmission at rates in excess of 10 MBPS. The outputs feature wide
common mode voltage range, making them suitable for party line
applications in noisy environments. The current limit and thermal
shutdown features protect the devices from line fault conditions.
These devices offer optimum performance when used with the
MC75173 and MC75175 line receivers.
Both devices are available in 16−pin plastic PDIP and 20−pin wide
body surface mount packages.
Features
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QUAD EIA−485 LINE DRIVERS
SOIC−20 WB
DW SUFFIX
CASE 751D
1
•
•
•
•
•
•
•
•
•
•
•
Meets EIA−485 Standard for Party Line Operation
Meets EIA−422−A and CCITT Recommendations V.11 and X.27
Operating Ambient Temperature: −40°C to +85°C
High Impedance Outputs
Common Mode Output Voltage Range: −7.0 to 12 V
Positive and Negative Current Limiting
Transmission Rates in Excess of 10 MBPS
Thermal Shutdown at 150°C Junction Temperature, (±20°C)
Single 5.0 V Supply
Pin Compatible with TI SN75172/4 and NS
mA96172/4
Interchangeable with MC3487 and AM26LS31 for EIA−422−A
Applications
•
Pb−Free Packages are Available*
MAXIMUM RATING
Rating
Power Supply Voltage
Input Voltage (Data, Enable)
Input Current (Data, Enable)
Applied Output Voltage, when in 3−State
Condition (V
CC
= 5.0 V)
Applied Output Voltage, when V
CC
= 0 V
Output Current
Storage Temperature
Symbol
V
CC
V
in
I
in
V
za
V
zb
I
O
T
stg
Value
−0.5, +7.0
+7.0
−24
−10, +14
±14
Self−Limiting
−65, +150
Unit
Vdc
Vdc
mA
Vdc
Vdc
−
°C
PDIP−16
P SUFFIX
CASE 648
1
MARKING DIAGRAMS
20
MC17517xBDW
AWLYYWWG
1
16
MC75174BP
AWLYYWWG
1
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Devices should not be operated at these limits. The “Recommended Operating
Conditions” table provides for actual device operation.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
x
A
WL
YY
WW
G
= 2 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
1
July, 2006 − Rev. 4
Publication Order Number:
MC75172B/D
MC75172B, MC75174B
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Input Voltage (All Inputs)
Output Voltage in 3−State Condition, or when V
CC
= 0 V
Output Current (Normal data transmission)
Operating Ambient Temperature (see text)
EIA−485
EIA−422
2. All limits are not necessarily functional concurrently.
Symbol
V
CC
V
in
V
cm
I
O
T
A
−40
0
Min
+4.75
0
−7.0
−65
Typ
+5.0
−
−
−
−
Max
+5.25
V
CC
+12
+65
+85
Unit
Vdc
Vdc
Vdc
mA
°C
ELECTRICAL CHARACTERISTICS
(−40°C
p
T
A
p
85°C, 4.75 V
p
V
CC
p
5.25 V, unless otherwise noted.)
Characteristic
Output Voltage
Single−Ended Voltage
I
O
= 0
High @ I
O
= −33 mA
Low @ I
O
= +33 mA
Differential Voltage
Open Circuit (I
O
= 0)
R
L
= 54
W
(Figure 1)
Change in Differential*, R
L
= 54
W
(Figure 1)
Differential Voltage, R
L
= 100
W
(Figure 1)
Change in Differential*, R
L
= 100
W
(Figure 1)
Differential Voltage, −7.0 V
p
V
cm
p
12 V (Figure 2)
Change in Differential*, −7.0 V
p
V
cm
p
12 V (Figure 2)
Offset Voltage, R
L
= 54
W
(Figure 1)
Change in Offset*, R
L
= 54
W
(Figure 1)
Output Current (Each Output)
Power Off Leakage, V
CC
= 0, −7.0 V
p
V
O
p
12 V
Leakage in 3−State Mode, −7.0 V
p
V
O
p
12 V
Short Circuit Current to Ground
Short Circuit Current, −7.0 V
p
V
O
p
12 V
Inputs
Low Level Voltage (Pins 4 & 12, MC75174B only)
Low Level Voltage (All Other Pins)
High Level Voltage (All Inputs)
Current @ V
in
= 2.7 V (All Inputs)
Current @ V
in
= 0.5 V (All Inputs)
Clamp Voltage (All Inputs, I
in
= −18 mA)
Thermal Shutdown Junction Temperature
Power Supply Current (Outputs Open, V
CC
= 5.25 V)
Outputs Enable
Outputs Disabled
Symbol
Min
Typ
Max
Unit
Vdc
V
O
V
OH
V
OL
⎥
V
OD1
⎜
⎥
V
OD2
⎜
⎥
DV
OD2
⎜
⎥
V
OD2A
⎜
⎥
DV
OD2A
⎜
⎥
V
OD3
⎜
⎥
DV
OD3
⎜
V
OS
⎥
DV
OS
⎜
I
O(off)
I
OZ
I
OSR
I
OS
V
IL(A)
V
IL(B)
V
IH
I
IH
I
IL
V
IK
T
jts
I
CC
−
−
60
30
70
40
0
−
−
1.5
1.5
−
−
−
1.5
−
−
−
−50
−50
−150
−250
0
0
2.0
−
−100
−1.5
−
−
4.0
1.6
3.4
2.3
5.0
2.2
5.0
−
5.0
2.9
5.0
0
0
−
−
−
−
−
0.2
−15
−
+150
6.0
−
−
6.0
5.0
200
−
200
5.0
200
−
200
+50
+50
+150
+250
0.7
0.8
V
CC
20
−
−
−
mA
Vdc
°C
mA
mVdc
Vdc
mVdc
Vdc
mVdc
Vdc
mVdc
mA
mA
Vdc
3. *V
in
switched from 0.8 to 2.0 V. Typical values determined at 25°C ambient and 5.0 V supply.
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2
MC75172B, MC75174B
TIMING CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V)
Characteristics
Propagation Delay − Input to Single−ended Output (Figure 3)
Output Low−to−High
Output High−to−Low
Propagation Delay − Input to Differential Output (Figure 4)
Input Low−to−High
Input High−to−Low
Differential Output Transition Time (Figure 4)
Skew Timing
⎜t
PLHD
− t
PHLD
⎜
for Each Driver
Max − Min t
PLHD
Within a Package
Max − Min t
PHLD
Within a Package
Enable Timing
Single−ended Outputs (Figure 5)
Enable to Active High Output
Enable to Active Low Output
Active High to Disable (using Enable)
Active Low to Disable (using Enable)
Enable to Active High Output (MC75172B only)
Enable to Active Low Output (MC75172B only)
Active High to Disable (using Enable, MC75172B only)
Active Low to Disable (using Enable, MC75172B only)
Differential Outputs (Figure 6)
Enable to Active Output
Enable to Active Output (MC75172B only)
Enable to 3−State Output
Enable to 3−State Output (MC75172B only)
Symbol
t
PLH
t
PHL
t
PLH(D)
t
PHL(D)
t
dr
, t
df
t
SK1
t
SK2
t
SK3
Min
−
−
−
−
−
−
−
−
Typ
23
18
15
17
19
0.2
1.5
1.5
Max
30
30
ns
25
25
25
−
−
−
ns
t
PZH(E)
t
PZL(E)
t
PHZ(E)
t
PLZ(E)
t
PZH(E)
t
PZL(E)
t
PHZ(E)
t
PLZ(E)
t
PZD(E)
t
PZD(E)
t
PDZ(E)
t
PDZ(E)
−
−
−
−
−
−
−
−
−
−
−
−
48
20
35
30
58
28
38
36
47
56
32
40
60
30
45
50
70
35
50
50
ns
−
−
−
−
ns
ns
Unit
ns
PIN CONNECTIONS
MC75172B
1A 1
1Y 2
NC 3
1Z 4
En 5
2Z 6
NC 7
2Y 8
2A 9
GND 10
DW Package
20 V
CC
19 4A
18 4Y
17 NC
16 4Z
15 En
14 3Z
13 NC
12 3Y
11 3A
1A 1
1Y 2
1Z 3
En 4
12
2Z 5
2Y 6
2A 7
GND 8
P Package
MC75174B
16 V
CC
15 4A
14 4Y
13 4Z
12 En
34
11 3Z
10 3Y
9 3A
1A 1
1Y 2
NC 3
1Z 4
En 5
12
2Z 6
NC 7
2Y 8
2A 9
GND 10
DW Package
20 V
CC
19 4A
18 4Y
17 NC
16 4Z
15 En
34
14 3Z
13 NC
12 3Y
11 3A
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3
MC75172B, MC75174B
V
CC
V
in
(0.8 or 2.0 V)
R
L
/2
V
OD2,A
R
L
/2
V
OS
V
in
(0.8 or 2.0 V)
V
CC
375
V
OD3
58
375
+
V
CM
= 12 to −7.0 V
Figure 1. V
DD
Measurement
Figure 2. Common Mode Test
3.0 V
V
CC
V
in
Y
Z
S.G.
Output Z
t
PHL
3.0 V
2.3 V
27
W
Output
15 pF
Output Y
3.0 V
3.0 V
V
OL
t
PLH
3.0 V
V
OH
V
in
1.5 V
t
PLH
t
PHL
1.5 V
0V
Figure 3. Propagation Delay, Single−Ended Outputs
3.0 V
V
CC
V
in
V
in
54
50 pF
V
OD
1.5 V
t
PLHD
1.5 V
0V
t
PHLD
1.5 V
50%
−1.5 V
t
df
S.G.
V
OD
1.5 V
50%
−1.5 V
t
dr
[4.6
V
NOTES:
1.S.G. set to: f
p
1.0 MHz; duty cycle = 50%; t
r
, t
f
,
p
5.0 ns.
2.t
SK1
=
⎥
t
PLHD
− t
PHLD
⎥
for each driver.
3.t
SK2
computed by subtracting the shortest t
PLHD
from the longest t
PLHD
of the 4 drivers within a package.
4.t
SK3
computed by subtracting the shortest t
PHLD
from the longest t
PHLD
of the 4 drivers within a package.
Figure 4. Propagation Delay, Differential Outputs
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