Blackfin
Embedded Processor
ADSP-BF539/ADSP-BF539F
FEATURES
1.0 V to 1.25 V core V
DD
with on-chip voltage regulation
3.0 V to 3.3 V I/O V
DD
Up to 3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free CSP_BGA package
Up to 533 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler friendly support
Advanced debug, trace, and performance monitoring
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and external
memory
PERIPHERALS
Parallel peripheral interface (PPI),
supporting ITU-R 656 video data formats
4 dual-channel, full-duplex synchronous serial ports, sup-
porting 16 stereo I
2
S channels
2 DMA controllers supporting 26 peripheral DMAs
4 memory-to-memory DMAs
Controller area network (CAN) 2.0B controller
Media transceiver (MXVR) for connection
to a MOST network
3 SPI-compatible ports
Three 32-bit timer/counters with PWM support
3 UARTs with support for IrDA
2 TWI controllers compatible with I
2
C industry standard
Up to 38 general-purpose I/O pins (GPIO)
Up to 16 general-purpose flag pins (GPF)
Real-time clock, watchdog timer, and 32-bit core timer
On-chip PLL capable of 0.5 to 64 frequency multiplication
Debug/JTAG interface
JTAG TEST AND EMULATION
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K 16-bit or 256K 16-bit flash memory
(ADSP-BF539F only)
Memory management unit providing memory protection
VOLTAGE REGULATOR
PERIPHERAL ACCESS BUS
PERIPHERAL ACCESS BUS
TWI0-1
CAN 2.0B
DMA CORE
BUS 2
GPIO
PORT
C
B
DMA
CONTROLLER1
DMA ACCESS BUS 1
INTERRUPT
CONTROLLER
WATCHDOG
TIMER
RTC
PPI
MXVR
SPI1-2
DMA ACCESS BUS 0
GPIO
PORT
D
L1 INSTRUCTION
MEMORY
L1 DATA
MEMORY
DMA
CONTROLLER 0
DMA
EXTERNAL
BUS 0
TIMER0-2
SPI0
UART0
SPORT0-1
UART1-2
GPIO
PORT
F
DMA CORE
BUS 1
GPIO
PORT
E
SPORT2-3
DMA
EXTERNAL
BUS 1
DMA CORE BUS 0
EXTERNAL PORT
FLASH, SDRAM CONTROL
16
512kB OR 1MB
FLASH MEMORY
(ADSP-BF539F ONLY)
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008
Analog Devices, Inc. All rights reserved.
ADSP-BF539/ADSP-BF539F
TABLE OF CONTENTS
General Description ................................................. 3
Low Power Architecture ......................................... 3
Automotive Products ............................................. 3
System Integration ................................................ 3
ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 4
DMA Controllers .................................................. 9
Real-Time Clock ................................................... 9
Watchdog Timer .................................................. 9
Timers ............................................................. 10
Serial Ports (SPORTs) .......................................... 10
Serial Peripheral Interface (SPI) Ports ...................... 10
2-Wire Interface ................................................. 11
UART Ports ...................................................... 11
Programmable I/O Pins ........................................ 11
Parallel Peripheral Interface ................................... 12
Controller Area Network (CAN) Interface ................ 13
Media Transceiver MAC layer (MXVR) ................... 13
Dynamic Power Management ................................ 13
Voltage Regulation .............................................. 15
Clock Signals ..................................................... 15
Booting Modes ................................................... 16
Instruction Set Description ................................... 17
Development Tools ............................................. 17
Designing an Emulator Compatible Processor Board ... 18
Example Connections and Layout Considerations ...... 18
Voltage Regulator Layout Guidelines ....................... 20
MXVR Board Layout Guidelines ............................ 19
Pin Descriptions .................................................... 21
Specifications ........................................................ 26
Operating Conditions ........................................... 26
Electrical Characteristics ....................................... 27
Absolute Maximum Ratings ................................... 28
Package Information ............................................ 28
ESD Sensitivity ................................................... 28
Timing Specifications ........................................... 29
Clock and Reset Timing ..................................... 30
Asynchronous Memory Read Cycle Timing ............ 31
Asynchronous Memory Write Cycle Timing ........... 33
SDRAM Interface Timing .................................. 35
External Port Bus Request and Grant Cycle Timing .. 36
Parallel Peripheral Interface Timing ...................... 38
Serial Ports Timing ........................................... 41
Serial Peripheral Interface Ports—Master Timing ..... 44
Serial Peripheral Interface Ports—Slave Timing ....... 45
General-Purpose Port Timing ............................. 46
Timer Cycle Timing .......................................... 47
JTAG Test And Emulation Port Timing ................. 48
MXVR Timing ................................................ 49
Output Drive Currents ......................................... 50
Power Dissipation ............................................... 52
Test Conditions .................................................. 52
Thermal Characteristics ........................................ 55
316-Ball CSP_BGA Ball Assignment ........................... 56
Outline Dimensions ................................................ 59
Surface-Mount Design .......................................... 60
Ordering Guide ..................................................... 60
REVISION HISTORY
2/08—Rev. 0 to Rev. A
Identifying pins CANRX and PC4 as 5 V-tolerant when config-
ured as an input and an open-drain when configured as an
output.
Rev. A |
Page 2 of 60 |
February 2008
ADSP-BF539/ADSP-BF539F
GENERAL DESCRIPTION
The ADSP-BF539/ADSP-BF539F processors are members of
the Blackfin
®
family of products, incorporating the Analog
Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin
processors combine a dual-MAC, state-of-the-art signal pro-
cessing engine, the advantages of a clean, orthogonal RISC-like
microprocessor instruction set, and single-instruction, multi-
ple-data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF539/ADSP-BF539F processors are completely
code compatible with other Blackfin processors, differing only
with respect to performance, peripherals, and on-chip memory.
Specific performance, peripherals, and memory configurations
are shown in
Table 1 on Page 3.
Table 1. Processor Features
Feature
SPORTs
UARTs
SPI
TWI
CAN
MXVR
PPI
Instruction
SRAM/Cache
Instruction
SRAM
Data
SRAM/Cache
Data SRAM
Scratchpad
Flash
Maximum
Speed Grade
Package
Option
ADSP-BF539 ADSP-BF539F4 ADSP-BF539F8
4
3
3
2
1
1
1
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes
Not
applicable
4
3
3
2
1
1
1
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes
256K
16-bit
4
3
3
2
1
1
1
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes
512K
16-bit
substantial reduction in power consumption, compared with
simply varying the frequency of operation. This translates into
longer battery life and lower heat dissipation.
AUTOMOTIVE PRODUCTS
Some ADSP-BF539/ADSP-BF539F models are available for
automotive applications with controlled manufacturing. Note
that these special models may have specifications that differ
from the general release models. For information on which
models are available for automotive applications, see
“Ordering
Guide” on page 60.
SYSTEM INTEGRATION
The ADSP-BF539/ADSP-BF539F processors are highly inte-
grated system-on-a-chip solutions for the next generation of
industrial and automotive applications including audio and
video signal processing. By combining advanced memory con-
figurations, such as on-chip flash memory, with industry-
standard interfaces with a high performance signal processing
core, users can develop cost-effective solutions quickly without
the need for costly external components. The system peripherals
include a MOST Network Media Transceiver (MXVR), three
UART ports, three SPI ports, four serial ports (SPORT), one
CAN interface, two 2-wire interfaces (TWI), four general-pur-
pose timers (three with PWM capability), a real-time clock, a
watchdog timer, a parallel peripheral interface, general-purpose
I/O, and general-purpose flag pins.
ADSP-BF539/ADSP-BF539F PROCESSOR
PERIPHERALS
The ADSP-BF539/ADSP-BF539F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see
Figure 1 on Page 1).
The general-purpose peripherals include functions such as
UART, timers with PWM (pulse-width modulation) and pulse
measurement capability, general-purpose flag I/O pins, a real-
time clock, and a watchdog timer. This set of functions satisfies
a wide variety of typical system support needs and is augmented
by the system expansion capabilities of the device. In addition to
these general-purpose peripherals, the ADSP-BF539/ADSP-
BF539F processors contain high speed serial and parallel ports
for interfacing to a variety of audio, video, and modem codec
functions. An MXVR transceiver transmits and receives audio
and video data and control information on a MOST automotive
multimedia network. A CAN 2.0B controller is provided for
automotive control networks. An interrupt controller manages
interrupts from the on-chip peripherals or external sources.
And power management control functions tailor the perfor-
mance and power characteristics of the processor and system to
many application scenarios.
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also four separate memory DMA
channels dedicated to data transfers between the processor’s
533 MHz
533 MHz
1066 MMACS 1066 MMACS
BC-316
BC-316
533 MHz
1066 MMACS
BC-316
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support, and leading edge signal
processing in one integrated package.
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and
performance. Blackfin processors are designed in a low power
and low voltage design methodology and feature dynamic
power management, the ability to vary both the voltage and fre-
quency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
Rev. A |
Page 3 of 60 |
February 2008
ADSP-BF539/ADSP-BF539F
various memory spaces, including external SDRAM and asyn-
chronous memory. Multiple on-chip buses running at up to
133 MHz provide enough bandwidth to keep the processor core
running along with activity on all of the on-chip and external
peripherals.
The ADSP-BF539/ADSP-BF539F processors include an on-chip
voltage regulator in support of the ADSP-BF539/ADSP-BF539F
processor dynamic power management capability. The voltage
regulator provides a range of core voltage levels from a single
2.7 V to 3.6 V input. The voltage regulator can be bypassed at
the user's discretion.
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that can be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
BLACKFIN PROCESSOR CORE
As shown in
Figure 2,
the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-bit, 16-bit, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
32
multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations, 16-
bit and 8-bit adds with clipping, 8-bit average operations, and 8-
bit subtract/absolute value/accumulate (SAA) operations. Also
provided are the compare/select and vector search instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
MEMORY ARCHITECTURE
The ADSP-BF539/ADSP-BF539F processors view memory as a
single unified 4G byte address space, using 32-bit addresses. All
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/per-
formance balance of some very fast, low latency on-chip
memory as cache or SRAM, and larger, lower cost and perfor-
mance off-chip memory systems. See
Figure 3.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 516M bytes of physical
memory.
The memory DMA controller provides high bandwidth data
movement capability. It performs block transfers of code or data
between the internal memory and the external memory spaces.
Rev. A |
Page 4 of 60 |
February 2008
ADSP-BF539/ADSP-BF539F
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
DA1
DA0
TO MEMORY
32
32
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
RAB
32
PREG
SD
LD1
LD0
32
32
32
32
32
ASTAT
SEQUENCER
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
BARREL
SHIFTER
16
8
8
8
16
8
DECODE
ALIGN
40
40
40
40
LOOP BUFFER
A0
A1
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Internal (On-Chip) Memory
The ADSP-BF539/ADSP-BF539F processor has three blocks of
on-chip memory providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of 80K bytes
SRAM, of which 16K bytes can be configured as a four-way set-
associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of up to 32K bytes each. Each memory bank
is configurable, offering both cache and SRAM functionality.
This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratch pad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 512M bytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
Flash Memory (ADSP-BF539F Only)
The ADSP-BF539F4 and ADSP-BF539F8 processors contain a
separate flash die, connected to the EBIU bus, within the pack-
age of the ADSP-BF539F processors.
Figure 4
shows how the
flash memory die and Blackfin processor die are connected.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
Rev. A |
Page 5 of 60 |
February 2008
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