www.fairchildsemi.com
FSDH321, FSDL321
Features
• Internal Avalanche Rugged Sense FET
• Consumes only 0.65W at 240VAC & 0.3W load with
Advanced Burst-Mode Operation
• Frequency Modulation for low EMI
• Precision Fixed Operating Frequency
• Internal Start-up Circuit
• Pulse by Pulse Current Limiting
• Abnormal Over Current Protection
• Over Voltage Protection
• Over Load Protection
• Internal Thermal Shutdown Function
• Auto-Restart Mode
• Under Voltage Lockout
• Low Operating Current (max 3mA)
• Adjustable Peak Current Limit
• Built-in Soft Start
Green Mode Fairchild Power Switch (FPS
TM
)
OUTPUT POWER TABLE
230VAC
±15%
(3)
PRODUCT
FSDL321
FSDH321
FSDL0165RN
FSDM0265RN
FSDH0265RN
FSDL0365RN
FSDM0365RN
FSDL321L
FSDH321L
FSDL0165RL
FSDM0265RL
FSDH0265RL
FSDL0365RL
FSDM0365RL
Adapt-
er
(1)
11W
11W
13W
16W
16W
19W
19W
11W
11W
13W
16W
16W
19W
19W
Open
Frame
(2)
17W
17W
23W
27W
27W
30W
30W
17W
17W
23W
27W
27W
30W
30W
85-265VAC
Adapt-
er
(1)
8W
8W
11W
13W
13W
16W
16W
8W
8W
11W
13W
13W
16W
16W
Open
Frame
(2)
12W
12W
17W
20W
20W
24W
24W
12W
12W
17W
20W
20W
24W
24W
Applications
• SMPS for STB, Low cost DVD
• Auxiliary Power for PC
• Adaptor for Charger
Description
The FSDx321(x stands for H, L) are integrated Pulse Width
Modulators (PWM) and Sense FETs specifically designed
for high performance offline Switch Mode Power Supplies
(SMPS) with minimal external components. Both devices
are integrated high voltage power switching regulators
which combine an avalanche rugged Sense FET with a cur-
rent mode PWM control block. The integrated PWM con-
troller features include: a fixed oscillator with frequency
modulation for reduced EMI, Under Voltage Lock Out
(UVLO) protection, Leading Edge Blanking (LEB), opti-
mized gate turn-on/turn-off driver, Thermal Shut Down
(TSD) protection, Abnormal Over Current Protection
(AOCP) and temperature compensated precision current
sources for loop compensation and fault protection circuitry.
When compared to a discrete MOSFET and controller or
RCC switching converter solution, the FSDx321 reduce total
component count, design size, weight and at the same time
increase efficiency, productivity, and system reliability. Both
devices are a basic platform well suited for cost effective
designs of flyback converters.
Table 1. Notes: 1. Typical continuous power in a non-ven-
tilated enclosed adapter measured at 50°C ambient. 2.
Maximum practical continuous power in an open frame
design at 50°C ambient. 3. 230 VAC or 100/115 VAC with
doubler.
Typical Circuit
AC
IN
DC
OUT
Vstr
Ipk
PWM
Vfb
Drain
Vcc
Source
Figure 1. Typical Flyback Application
Rev.1.0.2
©2004 Fairchild Semiconductor Corporation
FSDH321, FSDL321
Internal Block Diagram
Vcc
2
+
Vstr
5
Drain
6,7,8
I
start
Soft start
V
BURL
/V
BURH
-
8V/12V
V
BURH
Vcc
I
B_PEAK
Vcc
I
delay
Vcc
Vcc good
Freq.
Modulation
Vref
Internal
Bias
OSC
V
FB
3
I
FB
Normal
S
Q
PWM
Burst
R
Q
2.5R
I
pk
4
R
Gate
driver
LEB
V
SD
Vcc
S
Q
1 GND
AOCP
Vocp
Vovp
TSD
Vcc good
R
Q
Figure 2. Functional Block Diagram of FSDx321
2
FSDH321, FSDL321
Pin Definitions
Pin Number
1
Pin Name
GND
Pin Function Description
Sense FET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transform-
er winding, current is supplied from pin 5 (Vstr) via an internal switch during
startup (see Internal Block Diagram section). It is not until Vcc reaches the
UVLO upper threshold (12V) that the internal start-up switch opens and de-
vice power is supplied via the auxiliary transformer winding.
The feedback voltage pin is the non-inverting input to the PWM comparator.
It has a 0.9mA current source connected internally while a capacitor and op-
tocoupler are typically connected externally. A feedback voltage of 6V trig-
gers over load protection (OLP). There is a time delay while charging
between 3V and 6V using an internal 5uA current source, which prevents
false triggering under transient conditions but still allows the protection
mechanism to operate under true overload conditions.
Pin to adjust the current limit of the Sense FET. The feedback 0.9mA current
source is diverted to the parallel combination of an internal 2.8kΩ resistor
and any external resistor to GND on this pin to determine the current limit.
If this pin is tied to Vcc or left floating, the typical current limit will be 0.7A.
This pin connects directly to the rectified AC line voltage source. At start up
the internal switch supplies internal bias and charges an external storage
capacitor placed between the Vcc pin and ground. Once the Vcc reaches
12V, the internal switch is disabled.
The Drain pin is designed to connect directly to the primary lead of the trans-
former and is capable of switching a maximum of 650V. Minimizing the
length of the trace connecting this pin to the transformer will decrease leak-
age inductance.
2
Vcc
3
Vfb
4
Ipk
5
Vstr
6, 7, 8
Drain
Pin Configuration
8DIP
8LSOP
GND 1
Vcc 2
Vfb 3
Ipk 4
8 Drain
7 Drain
6 Drain
5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDH321, FSDL321
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Parameter
Maximum Vstr Pin Voltage
Maximum Drain Pin Voltage
Drain-Gate Voltage (R
GS
=1MΩ)
Gate-Source (GND) Voltage
Drain Current Pulsed
(1)
Continuous Drain Current (Tc=25°C)
Continuous Drain Current (Tc=100°C)
Single Pulsed Avalanche Energy
(2)
Maximum Supply Voltage
Input Voltage Range
Total Power Dissipation
Operating Junction Temperature.
Operating Ambient Temperature.
Storage Temperature Range.
Symbol
V
STR,MAX
V
DRAIN,MAX
V
DGR
V
GS
I
DM
I
D
I
D
E
AS
V
CC,MAX
V
FB
P
D
T
J
T
A
T
STG
Value
650
650
650
±20
1.5
0.7
0.32
10
20
−0.3
to Vstop
1.25
+150
-25 to +85
-55 to +150
Unit
V
V
V
V
A
DC
A
DC
A
DC
mJ
V
V
W
°C
°C
°C
Note:
1. Repetitive rating: Pulse width limited by maximum junction temperature
2. L = 24mH, starting Tj = 25°C
4
FSDH321, FSDL321
Electrical Characteristics (Sense FET Part)
(Ta = 25°C unless otherwise specified)
Parameter
Sense FET SECTION
Drain-Source Breakdown Voltage
Startup Voltage (Vstr) Breakdown
BV
DSS
BV
STR
V
GS
=0V, I
D
=50µA
V
CC
=0V, I
D
=1mA
V
DS
=Max. Rating,
V
GS
=0V
V
DS
=0.8Max. Rating,
V
GS
=0V, T
C
=125°C
V
GS
=10V, I
D
=0.5A
V
DS
=50V, I
D
=0.5A
V
GS
=0V, V
DS
=25V,
f=1MHz
V
DD
=0.5B V
DSS
,
I
D
=1.0A
(MOSFET switching time
is essentially
independent of
operating temperature)
V
GS
=10V, I
D
=1.0A,
V
DS
=0.5B V
DSS
(MOSFET switching time
is essentially
independent of operating
temperature)
650
650
-
-
-
1.0
-
-
-
-
-
-
-
-
-
-
720
720
-
-
14
1.3
162
18
3.8
9.5
19
33
42
7.0
3.1
0.4
-
-
25
200
19
-
-
-
-
-
-
-
-
-
-
-
nC
ns
pF
V
V
µA
µA
Ω
S
Symbol
Condition
Min.
Typ.
Max.
Unit
Zero Gate Voltage Drain Current
I
DSS
Static Drain-Source on Resistance
(Note)
R
DS(ON)
gfs
C
ISS
C
OSS
C
RSS
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Forward Trans conductance
(Note)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn on Delay Time
Rise Time
Turn Off Delay Time
Fall Time
Total Gate Charge
(Gate-Source + Gate-Drain)
Gate-Source Charge
Gate-Drain (Miller) Charge
Note:
1.
Pulse test: Pulse width
≤
300µS, duty
≤
2%
2.
1
S
= ---
-
R
5
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