ISP1161A1
USB single-chip host and device controller
Rev. 05 — 29 September 2009
Product data sheet
1. General description
The ISP1161A1 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and
Device Controller (DC). The Host Controller portion of the ISP1161A1 complies with
Universal Serial Bus Specification Rev. 2.0,
supporting data transfer at full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s). The Device Controller portion of the ISP1161A1
also complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at
full-speed (12 Mbit/s). These two USB controllers, the HC and the DC, share the same
microprocessor bus interface. They have the same data bus, but different I/O locations.
They also have separate interrupt request output pins, separate DMA channels that
include separate DMA request output pins and DMA acknowledge input pins. This makes
it possible for a microprocessor to control both the USB HC and the USB DC at the same
time.
The ISP1161A1 provides two downstream ports for the USB HC and one upstream port
for the USB DC. Each downstream port has an overcurrent (OC) detection input pin and
power supply switching control output pin. The upstream port has a V
BUS
detection input
pin.The ISP1161A1 also provides separate wake-up input pins and suspended status
output pins for the USB HC and the USB DC, respectively. This makes power
management flexible. The downstream ports for the HC can be connected with any USB
compliant devices and hubs that have USB upstream ports. The upstream port for the DC
can be connected to any USB compliant USB host and USB hubs that have USB
downstream ports.
The HC is adapted from the
Open Host Controller Interface Specification for USB Release
1.0a,
referred to as OHCI in the rest of this document.
The DC is compliant with most USB device class specifications such as Imaging Class,
Mass Storage Devices, Communication Devices, Printing Devices and Human Interface
Devices.
The ISP1161A1 is well suited for embedded systems and portable devices that require a
USB host only, a USB device only, or a combination of a configurable USB host and USB
device. The ISP1161A1 brings high flexibility to the systems that have it built-in. For
example, a system that uses an ISP1161A1 allows it not only to be connected to a PC
or USB hub with a USB downstream port, but also to be connected to a device that has a
USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse.
Therefore, the ISP1161A1 enables point-to-point connectivity between embedded
systems. An interesting application example is to connect an ISP1161A1 HC with an
ISP1161A1 DC.
Consider an example of an ISP1161A1 being used in a Digital Still Camera (DSC) design.
Figure 1
shows an ISP1161A1 being used as a USB DC.
Figure 2
shows an ISP1161A1
being used as a USB HC.
Figure 3
shows an ISP1161A1 being used as a USB HC and a
USB DC at the same time.
ISP1161A1
USB single-chip host and device controller
EMBEDDED SYSTEM
μP
μP
SYSTEM
MEMORY
PC
(host)
μP
bus I/F
ISP1161A1
HOST/
DEVICE
USB cable
USB I/F
USB I/F
USB device
DSC
004aaa173
Fig 1.
ISP1161A1 operating as a USB device.
EMBEDDED SYSTEM
μP
μP
SYSTEM
MEMORY
μP
bus I/F
ISP1161A1
HOST/
DEVICE
USB cable
USB I/F
PRINTER
(device)
USB I/F
DSC
USB host
004aaa174
Fig 2.
ISP1161A1 operating as a stand-alone USB host.
EMBEDDED SYSTEM
μP
μP
SYSTEM
MEMORY
PC
(host)
μP
bus I/F
DSC
PRINTER
(device)
ISP1161A1
HOST/
DEVICE
USB cable
USB I/F
USB device
USB host
004aaa175
USB cable
USB I/F
USB I/F
USB I/F
Fig 3.
ISP1161A1 operating as both USB host and device simultaneously.
ISP1161A1_5
© ST-ERICSSON 2009. All rights reserved.
Product data sheet
Rev. 05 — 29 September 2009
2 of 137
ISP1161A1
USB single-chip host and device controller
2. Features
Complies with
Universal Serial Bus Specification Rev. 2.0
The Host Controller portion of the ISP1161A1 supports data transfer at full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s)
The Device Controller portion of the ISP1161A1 supports data transfer at full-speed
(12 Mbit/s)
Combines the HC and the DC in a single chip
On-chip DC complies with most USB device class specifications
Both the HC and the DC can be accessed by an external microprocessor via separate
I/O port addresses
Selectable one or two downstream ports for the HC and one upstream port for the DC
High-speed parallel interface to most of the generic microprocessors and Reduced
Instruction Set Computer (RISC) processors such as:
Hitachi SuperH SH-3 and SH-4
MIPS-based RISC
ARM7, ARM9, StrongARM
Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC,
11.1 Mbyte/s data transfer rate between the microprocessor and the DC
Supports single-cycle and burst mode DMA operations
Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints for
the DC
Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes)
Endpoints with double buffering to increase throughput and ease real-time data
transfer for both DC transfers and HC isochronous (ISO) transactions
6 MHz crystal oscillator with integrated PLL for low EMI
Controllable LazyClock (100 kHz
±
50 %) output during ‘suspend’
Clock output with programmable frequency (3 MHz to 48 MHz)
Software controlled connection to USB bus (SoftConnect
1
) on upstream port for
the DC
Good USB connection indicator that blinks with traffic (GoodLink
2
) for the DC
Software selectable internal 15 kΩ pull-down resistors for HC downstream ports
Dedicated pins for suspend sensing output and wake-up control input for flexible
applications
Global hardware reset input pin and separate internal software reset circuits for HC
and DC
Operation from a 5 V or a 3.3 V power supply
Operating temperature range
−40 °C
to +85
°C
Available in two LQFP64 packages (SOT314-2 and SOT414-1).
1.
2.
SoftConnect is a trademark of ST-Ericsson.
GoodLink is a trademark of ST-Ericsson.
© ST-ERICSSON 2009. All rights reserved.
ISP1161A1_5
Product data sheet
Rev. 05 — 29 September 2009
3 of 137
ISP1161A1
USB single-chip host and device controller
3. Applications
Personal Digital Assistant (PDA)
Digital camera
Third-generation (3-G) phone
Set-Top Box (STB)
Information Appliance (IA)
Photo printer
MP3 jukebox
Game console.
4. Ordering information
Table 1.
Ordering information
Package description
Packing
Minimum
sellable quantity
1500 pieces
160 pieces
2000 pieces
250 pieces
Commercial
product code
ISP1161A1BDTM
ISP1161A1BDFA
ISP1161A1BMUM
ISP1161A1BMGA
LQFP64; 64 leads; body 10
×
10
×
1.4 mm 13 inch tape and reel non-dry pack
LQFP64; 64 leads; body 10
×
10
×
1.4 mm single tray non-dry pack
LQFP64; 64 leads; body 7
×
7
×
1.4 mm
LQFP64; 64 leads; body 7
×
7
×
1.4 mm
13 inch tape and reel dry pack
single tray dry pack
ISP1161A1_5
© ST-ERICSSON 2009. All rights reserved.
Product data sheet
Rev. 05 — 29 September 2009
4 of 137
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Product data sheet
Rev. 05 — 29 September 2009
© ST-ERICSSON 2009. All rights reserved.
ISP1161A1_5
5. Block diagram
6 MHz
to/from
microprocessor
H_WAKEUP
H_SUSPEND
NDP_SEL
40
42
33
2 to 7,
9 to 14,
16, 17,
63, 64
22
21
23
60
59
28
27
34
26
25
30
29
ALT RAM
ITL0
(PING RAM)
ITL1
(PONG RAM)
HOST CONTROLLER
XTAL2
44
XTAL1
43
46
47
54
55
H_PSW1
H_PSW2
H_OC1
H_OC2
POWER
SWITCHING
OVERCURRENT
DETECTION
16
D0 to D15
RD
CS
WR
A1
A0
DACK2
DACK1
EOT
DREQ2
DREQ1
INT2
INT1
ISP1161A1
HOST CONTROLLER
HOST/
DEVICE
AUTOMUX
50
USB
TRANSCEIVER
USB
TRANSCEIVER
51
52
53
H_DM1
H_DP1
H_DM2
H_DP2
USB bus
downstream
ports
HOST BUS
INTERFACE
Host bus
CLOCK
RECOVERY
PLL
4×
15 kΩ
DEVICE BUS
INTERFACE
Device bus
CLOCK
RECOVERY
GND
39
USB
TRANSCEIVER
48
49
D_WAKEUP
D_SUSPEND
37
36
DEVICE
CONTROLLER
D_VBUS
D_DM
D_DP
USB bus
upstream
port
USB single-chip host and device controller
RESET
32
POWER-ON
RESET
internal
reset
PING
RAM
PONG
RAM
SoftConnect
1.5 kΩ
3.3 V
DEVICE
CONTROLLER
GoodLink
38
PROGRAMMABLE
DIVIDER
41
61, 20
VCC
56
VOLTAGE
REGULATOR
1, 8, 15, 18,
35, 45, 62
7
3.3 V
internal
supply
57
58
24
19
ISP1161A1
DGND
AGND
Vreg(3.3)
2
GL
CLKOUT
n.c.
004aaa176
Vhold1
Vhold2
5 of 137
Fig 4.
Block diagram.