3D3220D-2.5 datasheet, PDF - EEWORLD Datasheet

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3D3220D-2.5: DescriptionMONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D3220); Categorylogic logic; File Size125KB，4 Pages; ManufacturerData Delay Devices; Environmental Compliance

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3D3220D-2.5 Overview

MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D3220)

3D3220D-2.5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOIC-14
Contacts	14
Reach Compliance Code	compli
Other features	INPUT TO FIRST TAP DELAY =7.5NS
series	3220
Input frequency maximum value (fmax)	125 MHz
JESD-30 code	R-PDSO-G14
length	8.695 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	10
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Maximum supply current (ICC)	5.5 mA
programmable delay line	NO
Prop。Delay @ Nom-Su	22.5 ns
Certification status	Not Qualified
Maximum seat height	1.82 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	30 ns
width	3.9 mm
Base Number Matches	1

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3D3220

MONOLITHIC 10-TAP

FIXED DELAY LINE

(SERIES 3D3220)

FEATURES

•

PACKAGES

N/C

GND

VDD

O10

All-silicon, low-power CMOS technology

14 VDD

TTL/CMOS compatible inputs and outputs

N/C

13 O1

Vapor phase, IR and wave solderable

12 O3

Auto-insertable (DIP pkg.)

11 O5

Low ground bounce noise

Leading- and trailing-edge accuracy

10 O7

Delay range:

0.75ns through 7000ns

9 O9

Delay tolerance:

2% or 0.5ns

GND

8 O10

Temperature stability:

±2%

typical (-40C to 85C)

3D3220-xx DIP

Vdd stability:

±1%

typical (3.0V-3.6V)

3D3220G-xx Gull-Wing

Minimum input pulse width:

15% of total delay

14-pin Gull-Wing available as drop-in

For mechanical dimensions, click

here

replacement for hybrid delay lines

For package marking details, click

here

3D3220D-xx SOIC

N/C

GND

VDD

N/C

O10

3D3220S-xx SOL

FUNCTIONAL DESCRIPTION

The 3D3220 10-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 0.75ns through 700ns. The

input is reproduced at the outputs without inversion, shifted in time as

per the user-specified dash number. The 3D3220 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

The all-CMOS 3D3220 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is

offered in a standard 14-pin auto-insertable DIP and space saving

surface mount 14-pin SOIC and 16-pin SOL packages.

PIN DESCRIPTIONS

O10

VDD

GND

Delay Line Input

Tap 1 Output (10%)

Tap 2 Output (20%)

Tap 3 Output (30%)

Tap 4 Output (40%)

Tap 5 Output (50%)

Tap 6 Output (60%)

Tap 7 Output (70%)

Tap 8 Output (80%)

Tap 9 Output (90%)

Tap 10 Output (100%)

+3.3 Volts

Ground

TABLE 1: PART NUMBER SPECIFICATIONS

DASH

NUMBER

-.75

-1

-1.5

-2

-2.5

-4

-5

-10

-20

-50

-100

-700

TOLERANCES

TOTAL

TAP-TAP

DELAY (ns)

6.75

0.5*

0.75

0.4

9.0

0.5*

1.0

0.5

13.5

0.5*

1.5

0.7

18.0

0.5*

2.0

0.8

22.5

0.5*

2.5

1.0

36.0

0.7*

4.0

1.3

50.0

1.0

5.0

1.5

100.0

2.0

10.0

2.0

200.0

4.0

20.0

4.0

500.0

50.0

1000

100

7000

140

700

140

Rec’d Max

Frequency

28.4 MHz

23.8 MHz

18.0 MHz

14.5 MHz

12.1 MHz

8.33 MHz

6.67 MHz

3.33 MHz

1.67 MHz

0.67 MHz

0.33 MHz

0.05 MHz

INPUT RESTRICTIONS

Absolute Max

Rec’d Min

Frequency

Pulse Width

166.7 MHz

17.6 ns

166.7 MHz

21.0 ns

166.7 MHz

27.8 ns

166.7 MHz

34.5 ns

125.0 MHz

41.2 ns

133.3 MHz

60.0 ns

66.7 MHz

75.0 ns

33.3 MHz

150 ns

16.7 MHz

300 ns

6.67 MHz

750 ns

3.33 MHz

1500 ns

0.48 MHz

10500 ns

Absolute Min

Pulse Width

3.00 ns

4.00 ns

6.00 ns

7.50 ns

15.0 ns

30.0 ns

75.0 ns

150 ns

1050 ns

2005

Data Delay Devices

* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns

1.0ns

NOTE: Any dash number between .75 and 700 not shown is also available as standard.

Doc #05001

12/22/05

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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