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74LVC541ADB,118

Description
Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin SSOP T/R
CategoryBuffer and line drives   
File Size241KB,14 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74LVC541ADB,118 Overview

Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin SSOP T/R

74LVC541ADB,118 Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)EAR99
Part StatusLTB
HTS8542.39.00.01
Logic FamilyLVC
Logic FunctionBuffer/Line Driver
Number of Elements per Chip1
Number of Channels per Chip8
Number of Inputs per Chip8
Number of Input Enables per Chip0
Number of Outputs per Chip8
Number of Output Enables per Chip2 Low
Bus HoldNo
PolarityNon-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns)3.5(Typ)@2.7V|2.9(Typ)@3.3V
Absolute Propagation Delay Time (ns)18.5
Process TechnologyCMOS
Input Signal TypeSingle-Ended
Output Type3-State
Maximum Low Level Output Current (mA)24
Maximum High Level Output Current (mA)-24
Minimum Operating Supply Voltage (V)1.2
Typical Operating Supply Voltage (V)1.8|2.5|3.3
Maximum Operating Supply Voltage (V)3.6
Tolerant I/Os (V)5
Typical Quiescent Current (uA)0.1
Maximum Quiescent Current (uA)40
Propagation Delay Test Condition (pF)50
Maximum Power Dissipation (mW)500
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)125
PackagingTape and Reel
Supplier PackageSSOP
Pin Count20
MountingSurface Mount
Package Height1.8(Max)
Package Length7.4(Max)
Package Width5.4(Max)
PCB changed20
74LVC541A
Rev. 5 — 13 March 2020
Octal buffer/line driver with 5 V tolerant inputs/outputs;
3-state
Product data sheet
1. General description
The 74LVC541A is an octal non-inverting buffer/line driver with 5 V tolerant inputs and outputs. The
3-state outputs are controlled by the output enable inputs OE1 and OE2.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied
to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V
applications.
2. Features and benefits
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC541AD
74LVC541ADB
74LVC541APW
74LVC541ABQ
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
SO20
SSOP20
TSSOP20
DHVQFN20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1

74LVC541ADB,118 Related Products

74LVC541ADB,118 74LVC541AD,112 74LVC541AD,118 74LVC541ABQ,115 74LVC541APW,118 74LVC541ADB,112 74LVC541APW,112
Description Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin SSOP T/R Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin SO Bulk Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin SO T/R Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin DHVQFN EP T/R Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin TSSOP T/R Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin SSOP Bulk Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin TSSOP Bulk
EU restricts the use of certain hazardous substances Compliant - - Compliant Compliant Compliant Compliant
ECCN (US) EAR99 - - EAR99 EAR99 EAR99 EAR99
Part Status LTB - - Active Active Obsolete LTB
HTS 8542.39.00.01 - - 8542.39.00.01 8542.39.00.01 8542.39.00.01 8542.39.00.01
Logic Family LVC - - LVC LVC LVC LVC
Logic Function Buffer/Line Driver - - Buffer/Line Driver Buffer/Line Driver Buffer/Line Driver Buffer/Line Driver
Number of Elements per Chip 1 - - 1 1 1 1
Number of Channels per Chip 8 - - 8 8 8 8
Number of Inputs per Chip 8 - - 8 8 8 8
Number of Outputs per Chip 8 - - 8 8 8 8
Number of Output Enables per Chip 2 Low - - 2 Low 2 Low 2 Low 2 Low
Bus Hold No - - No No No No
Polarity Non-Inverting - - Non-Inverting Non-Inverting Non-Inverting Non-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns) 3.5(Typ)@2.7V|2.9(Typ)@3.3V - - 3.5(Typ)@2.7V|2.9(Typ)@3.3V 2.9(Typ)@3.3V|3.5(Typ)@2.7V 2.9(Typ)@3.3V|3.5(Typ)@2.7V 2.9(Typ)@3.3V|3.5(Typ)@2.7V
Absolute Propagation Delay Time (ns) 18.5 - - 18.5 18.5 18.5 18.5
Process Technology CMOS - - CMOS CMOS CMOS CMOS
Input Signal Type Single-Ended - - Single-Ended Single-Ended Single-Ended Single-Ended
Output Type 3-State - - 3-State 3-State 3-State 3-State
Maximum Low Level Output Current (mA) 24 - - 24 24 24 24
Maximum High Level Output Current (mA) -24 - - -24 -24 -24 -24
Minimum Operating Supply Voltage (V) 1.2 - - 1.2 1.2 1.2 1.2
Typical Operating Supply Voltage (V) 1.8|2.5|3.3 - - 1.8|2.5|3.3 3.3|2.5|1.8 3.3|2.5|1.8 3.3|2.5|1.8
Maximum Operating Supply Voltage (V) 3.6 - - 3.6 3.6 3.6 3.6
Tolerant I/Os (V) 5 - - 5 5 5 5
Typical Quiescent Current (uA) 0.1 - - 0.1 0.1 0.1 0.1
Maximum Quiescent Current (uA) 40 - - 40 40 40 40
Propagation Delay Test Condition (pF) 50 - - 50 50 50 50
Maximum Power Dissipation (mW) 500 - - 500 500 500 500
Minimum Operating Temperature (°C) -40 - - -40 -40 -40 -40
Maximum Operating Temperature (°C) 125 - - 125 125 125 125
Packaging Tape and Reel - - Tape and Reel Tape and Reel Bulk Bulk
Supplier Package SSOP - - DHVQFN EP TSSOP SSOP TSSOP
Pin Count 20 - - 20 20 20 20
Mounting Surface Mount - - Surface Mount Surface Mount Surface Mount Surface Mount
Package Height 1.8(Max) - - 0.88 0.95(Max) 1.8(Max) 0.95(Max)
Package Length 7.4(Max) - - 4.5 6.6(Max) 7.4(Max) 6.6(Max)
Package Width 5.4(Max) - - 2.5 4.5(Max) 5.4(Max) 4.5(Max)
PCB changed 20 - - 20 20 20 20
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