AT45DB321D
32Mb, 2.5V or 2.7V
DataFlash
DATASHEET
(NOT RECOMMENDED FOR NEW DESIGNS. USE AT45DB321E.)
Features
●
Single 2.5V - 3.6V or 2.7V - 3.6V supply
●
RapidS
™
serial interface: 66MHz maximum clock frequency
●
SPI compatible modes 0 and 3
●
User configurable page size
●
512 bytes per page
●
528 bytes per page
●
Page size can be factory preconfigured for 512 bytes
●
Page program operation
●
Intelligent programming operation
●
8,192 pages (512/528 bytes/page) main memory
●
Flexible erase options
●
●
●
●
Page erase (512 bytes)
Block erase (4KB)
Sector erase (64KB)
Chip erase (32Mb)
●
Two SRAM data buffers (512/528 bytes)
●
Allows receiving data while reprogramming the flash array
●
Continuous read capability through entire array
●
Ideal for code shadowing applications
●
Low power dissipation
●
7mA active read current ,typical
●
25µA standby current, typical
●
15µA deep power down, typical
●
Hardware and software data protection features
●
Individual sector
●
Sector lockdown for secure code and data storage
●
Individual sector
●
Security: 128-byte security register
●
64-byte user programmable space
●
Unique 64-byte device identifier
●
JEDEC standard manufacturer and device ID read
●
100,000 program/erase cycles per page, minimum
●
Data retention: 20 years
●
Industrial temperature range
●
Green (Pb/halide-free/RoHS compliant) packaging options
3597U–DFLASH–11/2017
1.
Description
The AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital
voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the RapidS serial interface for
applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz.
The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory,
the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data while a
page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM (electrically
erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-contained,
three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple
address lines and a parallel interface, DataFlash
®
devices use a RapidS serial interface to sequentially access its data. The
simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability,
minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial
applications where high density, low pin count, low voltage and low power are essential.
To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The
device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is
enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output
(SO), and serial clock (SCK) lines.
All programming and erase cycles are self timed.
Figure 1-1.
Pin configurations and pinouts.
MLF
(1)
(VDFN)
Top View
SOIC
Top View
8
7
6
5
SI
SCK
RESET
CS
Note:
1.
1
2
3
4
SO
GND
VCC
WP
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
The metal pad on the bottom of
the MLF package is floating.
This pad can be a “No Connect” or
connected to GND.
BGA Package Ball-out
Top View
TSOP: Type 1
Top View
1
2
3
4
5
A
B
C
NC
NC
NC
NC
NC
NC
SCK
GND
VCC
NC
CS
RDY/BSY WP
NC
D
NC
SO
SI
RESET
NC
E
NC
NC
NC
NC
NC
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Note:
TSOP package is not recommended for new designs.
Future die shrinks will support 8-pin packages only.
AT45DB321D [DATASHEET]
3597U–DFLASH–11/2017
2
Table 1-1.
Pin Configurations
Asserted
State
Symbol
Name and Function
Type
CS
Chip Select:
Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not deep power-
down mode), and the output pin (SO) will be in a high-impedance state. When the device
is deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
Low
Input
SCK
Serial Clock:
This pin is used to provide a clock to the device, and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI
pin are always latched on the rising edge of SCK, while output data on the SO pin are
always clocked out on the falling edge of SCK.
Serial Input:
The SI pin is used to shift data into the device. The SI pin is used for all data
input, including command and address sequences. Data on the SI pin are always latched
on the rising edge of SCK.
Serial Output:
The SO pin is used to shift data out from the device. Data on the SO pin
are always clocked out on the falling edge of SCK.
Write Protect:
When the WP pin is asserted, all sectors specified for protection by the
sector protection register will be protected against program and erase operations,
regardless of whether the enable sector protection command has been issued or not. The
WP pin functions independently of the software controlled protection method. After the
WP pin goes low, the content of the sector protection register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the
device will simply ignore the command and perform no operation. The device will return to
the idle state once the CS pin has been deasserted. The enable sector protection
command and sector lockdown command, however, will be recognized by the device
when the WP pin is asserted.
The WP pin is internally pulled high, and may be left floating if hardware controlled
protection will not be used. However, it is recommended that the WP pin also be
externally connected to V
CC
whenever possible.
–
Input
SI
–
Input
SO
WP
–
Low
Output
Input
RESET
Reset:
A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, and so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized, it is
recommended that the RESET pin be driven high externally.
Low
Input
RDY/BUSY
Ready/Busy:
This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operations, and page-to-buffer transfers.
The busy status indicates that the flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
–
Output
V
CC
Device Power Supply:
The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be
attempted.
–
Power
GND
Ground:
The ground reference for the power supply. GND should be connected to the
system ground.
–
Ground
AT45DB321D [DATASHEET]
3597U–DFLASH–11/2017
3
Figure 1-2. Block Diagram
WP
Flash Memory Array
Page (512-/528-bytes)
Buffer 1 (512-/528-bytes)
Buffer 2 (512-/528-bytes)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O Interface
SI
SO
2.
Memory Array
To provide optimal flexibility, the AT45DB321D memory array is divided into three levels of granularity comprising sectors,
blocks, and pages. The
“Memory Architecture Diagram”
illustrates the breakdown of each level, and details the number of
pages per sector and block. All program operations to the DataFlash device occur on a page-by-page basis. The erase
operations can be performed at the chip, sector, block, or page level.
Figure 2-1. Memory Architecture Diagram
Sector Architecture
Sector 0a = 8 pages
4,096/4,224 bytes
Block Architecture
Sector 0a
Block 0
Block 1
Block 2
Page Architecture
8 Pages
Page 0
Page 1
Sector 0b = 120 pages
61,440/63,360 bytes
Sector 0b
Block 0
Page 6
Block 14
Page 7
Page 8
Page 9
Sector 1 = 128 pages
65,536/67,584 bytes
Block 15
Block 17
Sector 2 = 128 pages
65,536/67,584 bytes
Sector 1
Block 1
Block 16
Page 14
Page 15
Block 30
Block 31
Block 32
Page 16
Page 17
Page 18
Sector 62 = 128 pages
65,536/67,584 bytes
Block 33
Sector 63 = 128 pages
65,536/67,584 bytes
Block 1,022
Block 1,023
Page 8,190
Page 8,191
Block = 4,096/4,224 bytes
Page = 512/528 bytes
AT45DB321D [DATASHEET]
3597U–DFLASH–11/2017
4
3.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes
are contained in
Table 13-1 on page 24
through
Table 13-7 on page 27.
A valid instruction starts with the falling edge of CS,
followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low,
toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are transferred with the most-significant bit (msb) first.
Buffer addressing for the standard DataFlash page size (528 bytes) is referenced in the datasheet using the terminology BFA9
- BFA0 to denote the ten address bits required to designate a byte address within a buffer. Main memory addressing is
referenced using the terminology PA12 - PA0 and BA9 - BA0, where PA12 - PA0 denotes the 13 address bits required to
designate a page address and BA9 - BA0 denotes the ten address bits required to designate a byte address within the page.
For a “power of two” binary page size (512 bytes), the buffer addressing is referenced in the datasheet using the conventional
terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology A21 - A0, where A21 - A9 denotes the 13 address bits required to designate a
page address and A8 - A0 denotes the nine address bits required to designate a byte address within a page.
4.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers.
The DataFlash device supports RapidS protocols for Mode 0 and Mode 3. Please refer to
Section 22., Detailed Bit-level Read
Waveform – RapidS Serial Interface Mode 0/Mode 3
diagrams in this datasheet for details on the clock cycle sequences for
each mode.
4.1
Continuous Array Read (Legacy Command: E8H): Up to 66MHz
By supplying an initial starting address for the main memory array, the continuous array read command can be utilized to
sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash device incorporates an internal address counter that will
automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address
sequences. To perform a continuous read from the standard DataFlash page size (528 bytes), an opcode of E8H must be
clocked into the device, followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four
“don’t care” bytes. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory array
to read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the page. To
perform a continuous read from the binary page size (512-bytes), the opcode (E8H) must be clocked into the device followed by
three address bytes and four don’t care bytes. The first 13 bits (A21 - A9) of the 22-bit sequence specify which page of the main
memory array to read, and the last 9 bits (A8 - A0) of the 22-bit address sequence specify the starting byte address within the
page. The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care
bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data.
When the end of a page in main memory is reached during a continuous array read, the device will continue reading at the
beginning of the next page, with no delays incurred during the page boundary crossover (the crossover from the end of one
page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue
reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred
when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK
frequency allowable for the continuous array read is defined by the f
CAR1
specification. The continuous array read bypasses
both data buffers and leaves the contents of the buffers unchanged.
4.2
Continuous Array Read (High Frequency Mode: 0BH): Up to 66MHz
This command can be used with the serial interface to read the main memory array sequentially in high-speed mode for any
clock frequency up to the maximum specified by f
CAR1
. To perform a continuous read array with the page size set to 528 bytes,
CS must first be asserted, and then a 0BH opcode must be clocked into the device, followed by three address bytes and a
dummy byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory array to
read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the page. To
perform a continuous read with the page size set to 512 bytes, the 0BH opcode must be clocked into the device, followed by
three address bytes (A21 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result
in data being output on the SO (serial output) pin.
AT45DB321D [DATASHEET]
3597U–DFLASH–11/2017
5
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