USE GAL DEVICES FOR NEW DESIGNS
FINAL
COM’L: H-7/10/15/20
IND: H-7/10/15/20
PALCE20RA10 Family
DISTINCTIVE CHARACTERISTICS
s
Low power at 100 mA I
CC
s
As fast as 7.5 ns maximum propagation delay
and 100 MHz f
MAX
(external)
s
Individually programmable asynchronous
clock, preset, reset, and enable
s
Registered or combinatorial outputs
s
Programmable polarity
s
Programmable replacement for high-speed
CMOS or TTL logic
Lattice Semiconductor
24-Pin Asynchronous EE CMOS Programmable Array Logic
s
TTL-level register preload for testability
s
Extensive third-party software and programmer
support through FusionPLD partners
s
24-pin PDIP and 28-pin PLCC packages save
space
s
7.5 ns, 10 ns, and 15 ns versions utilize split
leadframes for improved performance
GENERAL DESCRIPTION
The PALCE20RA10 is an advanced PAL device built
with low-power, high-speed, electrically-erasable
CMOS technology. The PALCE20RA10 offers asyn-
chronous clocking for each of the ten flip-flops in the de-
vice. The ten macrocells feature programmable clock,
preset, reset, and enable, and all can operate
asynchronously to other macrocells in the same device.
The PALCE20RA10 also has flip-flop bypass, allowing
any combination of registered and combinatorial
outputs.
The PALCE20RA10 utilizes the familiar sum-of-prod-
ucts (AND/OR) architecture that allows users to imple-
ment complex logic functions easily and efficiently.
Multiple levels of combinatorial logic can always be re-
duced to sum-of-products form, taking advantage of the
very wide input gates available in PAL devices.
The equations are programmed into the device through
floating-gate cells in the AND logic array that can be
erased electrically.
BLOCK DIAGRAM
Output
Enable
Dedicated
Inputs
Preload
10
I
9
– I
0
Programmable AND Array
40 x 80
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
Enable
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Preload
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
15434H-1
Amendment
/0
2-184
Publication#
15434
Rev.
H
Issue Date:
February 1996
CONNECTION DIAGRAMS
Top View
SKINNYDIP
I
1
PLCC JEDEC
VCC
PL
I
0
NC
I/O
9
I/O
8
PL
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
OE
I
2
I
3
I
4
NC
I
5
I
6
I
7
5
6
7
8
9
10
11
12 13 14 15 16 17 18
I
8
I/O
0
GND
I/O
1
NC
OE
I
9
4
3
2
1 28 27 26
25
24
23
22
21
20
19
I/O
7
I/O
6
I/O
5
NC
I/O
4
I/O
3
I/O
2
15434H-2
15434H-3
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
GND
I
I/O
NC
OE
PL
V
CC
=
=
=
=
=
=
=
Ground
Input
Input/Output
No Connect
Output Enable
Preload
Supply Voltage
PALCE20RA10 Family
2-185
ORDERING INFORMATION
Commercial and Industrial Products
Programmable logic products for commercial and industrial applications are available with several ordering options. The
order number (Valid Combination) is formed by a combination of:
PAL CE 20 RA 10 H -7
J
I
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
RA = Registered Asynchronous
NUMBER OF OUTPUTS
POWER
H = Half Power (I
CC
= 100 mA)
SPEED
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-15 = 15 ns t
PD
-20 = 20 ns t
PD
OPERATING CONDITIONS
C = Commercial (0
°
C to +75
°
C)
I = Industrial (–40
°
C to +85
°
C)
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
Valid Combinations
PALCE20RA10H-7
PALCE20RA10H-10
PALCE20RA10H-15
PALCE20RA10H-20
JC, JI
PC, JC, PI, JI
Valid Combinations
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
your local sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
2-186
PALCE20RA10H-7/10/15/20 (Com’l, Ind)
Commercial and Industrial Products
PL
OE
S
0
AP
D Q
PL
P
AR
1
Output
0
15434H-5
Figure 1. PALCE20RA10 Macrocell
FUNCTIONAL DESCRIPTION
The PALCE20RA10 has ten dedicated input lines and
ten programmable I/O macrocells. The Registered
Asynchronous (RA) macrocell is shown in Figure 1.
PL
serves as global register preload and
OE
serves as
global output enable. Programmable output polarity is
available to provide user-programmable output polarity
for each individual macrocell.
The programmable functions in the PALCE20RA10 are
automatically configured from the user’s design specifi-
cation, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user’s desired function.
Programmable Clock
The clock input to each flip-flop comes from the pro-
grammable array, allowing any flip-flop to be clocked
independently if desired.
AP
D Q
AR
Registered/Active Low
Combinatorial/Active Low
Programmable Preset and Reset
In each macrocell, two product lines are dedicated to
asynchronous preset and asynchronous reset. If the
preset product line is HIGH, the Q output of the register
becomes a logic 1 and the output pin will be a logic 0. If
the reset product line is HIGH, the Q output of the regis-
ter becomes a logic 0 and the output pin will be logic 1.
The operation of the programmable preset and reset
overrides the clock.
AP
D Q
AR
Registered/Active High
Combinatorial/Active High
15434H-6
Combinatorial/Registered Outputs
If both the preset and reset product lines are HIGH, the
flip-flop is bypassed and the output becomes combina-
torial. Otherwise, the output is from the register. Each
output can be configured to be combinatorial or
registered.
Figure 2. Macrocell Configurations
PALCE20RA10 Family
2-187
Three-State Outputs
The devices provide a product term dedicated to local
output control. There is also a global output control pin.
The output is enabled if both the global output control
pin is LOW and the local output control product term is
HIGH. If the global output control pin is HIGH, all outputs
will be disabled. If the local output control product term is
LOW, then that output will be disabled.
Output Register Preload
The output registers on the PALCE20RA10 can be
preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature
allows direct loading of arbitrary states, making it unnec-
essary to cycle through long test vector sequences to
reach a desired state. In addition, transitions from illegal
states can be verified by loading illegal states and ob-
serving proper recovery. Register preload is controlled
by a TTL-level signal, making it a convenient board-level
initialization function. Details on output register preload
can be found on page 16.
Security Bit
A security bit is also provided to prevent unauthorized
copying of PAL device patterns. Once the bit is pro-
grammed, the circuitry enabling verification is perma-
nently disabled, and the array will read as if every bit is
programmed. With verification not operating, it is impos-
sible to simply copy the PAL device pattern on a PAL de-
vice programmer. The security bit can only be erased in
conjunction with the entire pattern.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable
system initialization. Registered outputs of the
PALCE20RA10 will be HIGH due to the output inverter.
The state of combinatorial outputs will be a function of
the logic. Details on power-up reset can be found on
page 16.
Programmable Polarity
The outputs can be programmed either active-LOW or
active-HIGH. This is represented by the Exclusive-OR
gate shown in the PALCE20RA10 logic diagram. When
the output polarity bit is programmed, the lower input to
the Exclusive-OR gate is HIGH, so the output is active-
HIGH. Similarly when the output polarity bit is
unprogrammed, the output is active-LOW. The pro-
grammable output polarity feature allows the user a
higher degree of flexibility when writing equations.
Quality and Testability
The PALCE20RA10 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming yields and post-programming functional
yields in the industry.
Programming and Erasing
The PALCE20RA10 can be programmed on standard
logic programmers. Approved programmers are listed
at the end of this databook. It also may be erased to re-
set a previously configured device back to its virgin
state. Erasure is automatically performed by the pro-
gramming hardware. No special erase operation is re-
quired.
Technology
The high-speed PALCE20RA10 is fabricated with
Our advanced electrically erasable (EE) CMOS proc-
ess. The array connections are formed with proven EE
cells. Inputs and outputs are designed to be compatible
with TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
2-188
PALCE20RA10 Family
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