SI5317B-C-GMR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> SI5317B-C-GMR

SI5317B-C-GMR: DescriptionClock Generator, 350MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，46 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric Compare View All

SI5317B-C-GMR Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	SI5317B-C-GMR	-	-	View	Buy Now

SI5317B-C-GMR Overview

Clock Generator, 350MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

SI5317B-C-GMR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFN
package instruction	HVQCCN, LCC36,.25SQ,20
Contacts	36
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	CAN ALSO OPERATES AT 2.5V, 3.3V SUPPLY
JESD-30 code	S-XQCC-N36
length	6 mm
Number of terminals	36
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	350 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC36,.25SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8/3.3 V
Master clock/crystal nominal frequency	711 MHz
Certification status	Not Qualified
Maximum seat height	0.95 mm
Maximum slew rate	279 mA
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

Preview

Download Datasheet

View All

S i531 7

I N

-C

O N T R O L L E D

1–711 MH

I T T E R

L E A N I N G

L O C K

Features



Provides jitter attenuation for any clock



frequency

One clock input / two clock outputs



Input/output frequency range:

1–711 MHz



Ultra low jitter: 300 fs

(12 kHz–20 MHz) typical



Simple pin control interface



Selectable loop bandwidth for jitter

attenuation: 60 Hz–8.4 kHz



Meets OC-192 GR-253-CORE jitter



specifications

Selectable output clock signal

format: LVPECL, LVDS, CML or

CMOS

Single supply: 1.8, 2.5, or 3.3 V

Loss of lock and loss of signal

alarms

VCO freeze during LOS/LOL

On-chip voltage regulator with high

PSRR

Small size: 6 x 6 mm, 36-QFN

Wide temperature range: –40 to

+85 ºC

Ordering Information:

See page 40.

Applications



Data converter clocking

Wireless infrastructure

Networking, SONET/SDH



Switches and routers

Medical instrumentation

Test and measurement

Pin Assignments

Description

The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications

that require jitter attenuation without clock multiplication. The Si5317 accepts a

single clock input ranging from 1 to 711 MHz and generates two low jitter clock

outputs at the same frequency. The clock frequency range and loop bandwidth are

selectable from a simple look-up table. The Si5317 is based on Silicon

Laboratories' 3rd-generation DSPLL

technology, which provides jitter attenuation

on any frequency in a highly integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The DSPLL loop bandwidth is user

selectable, providing jitter performance optimization at the application level.

Functional Block Diagram

Rev. 1.1 4/11

Si5317

Si5317

A B L E O F

O N T E N T S

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9

1.2. Three-Level Input Pins (Example with External Resistors) . . . . . . . . . . . . . . . . . . . . .9

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.1. Frequency Range Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.2. Output Skew Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.3. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.5. VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.1. Input Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.2. Output Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

5. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

7. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

7.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

8. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

9. Pin Descriptions: Si5317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

11. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

12. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13. Si5317 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Rev. 1.1

SI5317B-C-GMR Related Products

	SI5317B-C-GMR	SI5317A-C-GMR	SI5317C-C-GM	SI5317C-C-GMR
Description	Clock Generator, 350MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36	Clock Generator, 711MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36	Clock Generator, 200MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36	Clock Generator, 200MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
Is it Rohs certified?	conform to	conform to	conform to	conform to
Parts packaging code	QFN	QFN	QFN	QFN
package instruction	HVQCCN, LCC36,.25SQ,20	HVQCCN, LCC36,.25SQ,20	HVQCCN, LCC36,.25SQ,20	HVQCCN, LCC36,.25SQ,20
Contacts	36	36	36	36
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
Other features	CAN ALSO OPERATES AT 2.5V, 3.3V SUPPLY	CAN ALSO OPERATES AT 2.5V, 3.3V SUPPLY	CAN ALSO OPERATES AT 2.5V, 3.3V SUPPLY	CAN ALSO OPERATES AT 2.5V, 3.3V SUPPLY
JESD-30 code	S-XQCC-N36	S-XQCC-N36	S-XQCC-N36	S-XQCC-N36
length	6 mm	6 mm	6 mm	6 mm
Number of terminals	36	36	36	36
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Maximum output clock frequency	350 MHz	711 MHz	200 MHz	200 MHz
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC36,.25SQ,20	LCC36,.25SQ,20	LCC36,.25SQ,20	LCC36,.25SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.8/3.3 V	1.8/3.3 V	1.8/3.3 V	1.8/3.3 V
Master clock/crystal nominal frequency	711 MHz	711 MHz	711 MHz	711 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	0.95 mm	0.95 mm	0.95 mm	0.95 mm
Maximum slew rate	279 mA	279 mA	279 mA	279 mA
Maximum supply voltage	1.89 V	1.89 V	1.89 V	1.89 V
Minimum supply voltage	1.71 V	1.71 V	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	6 mm	6 mm	6 mm	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER
Base Number Matches	1	1	1	1

Recommended Resources

PT2103 typical application circuit

Phase shift signal generator circuit using VMOS transistors

Mutual aid housekeeping alarm circuit

Bidirectional thyristor stepless dimming and speed regulation circuit

Wien bridge sine oscillator circuit diagram

Double stabilized power supply composed of LM309K

Good resources of the week (power supply category) second week of March: :) Good resources of the week (power supply category) Second week of March [url=https://download.eeworld.com.cn/detail/lilibin/560147]A high-frequency power supply device for wireless power transmissi...; okhxyyo Power technology

Design of power inductors: Haha , let me share my information with you (internal information of the company)...; haihaiwang PCB Design

Problems with nop instructions in atmel studio6: I recently started using atmel studio 6 and encountered a problem. I want to use asm("nop"); a function with no operation, but I don't know which header file it is? Please give me some advice,,,...; mirchell Microchip MCU

Only when this actually happens can we say that China is truly "prosperous.": http://www.eet-china.com/ART_8800669122_617693_NT_26f95982.HTM...; wangfuchong Talking

【Call for papers】51 single-chip microcomputer from entry to... to just getting started: Hey, actually "51 Single-Chip Microcomputer From Beginner to Master" is my introduction to single-chip microcomputers. In fact, this title is nothing new, and there are a lot of similar books. But my ...; anqi90 51mcu

[Help] "Statement not ended" when reading and writing files in eVB?: The source code is as follows: Private Sub Form_Load() Dim word, meaning As String Open "words.dat" For Input Access Read As #1 Do While Not EOF(1) Input #1, word, meaning Loop Close #1 End Sub When r...; eedede Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components