DATA SHEET
MARCH 1999
LXP600A, LXP602 and LXP604
Low Jitter Clock Adapters (CLADs)
General Description
The LXP600A, LXP602 and LXP604 Clock Adapters
(CLADs) incorporate Level One’s patented frequency
conversion circuitry. The LXP600A and LXP602 convert
a 1.544 MHz input clock to a 2.048 MHz output clock, or
vice versa. The LXP604 converts between 1.544 MHz and
4.096 MHz. Each CLAD produces two different high
frequency output (HFO) clocks for applications which
require a higher-than-baud rate backplane or system clock.
Level One’s patented locking method enables the CLAD to
perform frequency conversion with no external
components, while generating very little jitter on the output
clock. The conversion is digitally controlled so the output
clock (CLKO) is as accurate as the input clock (CLKI), and
the two clocks are frequency-locked together. When an
input frame sync pulse (FSI) is provided, the CLAD also
phase-locks CLKI and CLKO together, and locks the
output frame sync pulse (FSO) to FSI.
Revision 1.1
Features
• Generates a 1.544 MHz clock and its frame sync from
a 2.048 MHz or 4.096 MHz clock and its frame sync,
or vice versa
• Low output jitter meets AT&T Publication 62411 for
1.544 MHz, and ITU Recommendation G.823 for
2.048 MHz
• Digital control of frequency conversion process
• No external components
• Available in 8-pin plastic DIP and 16-pin SOIC
• Pin-selectable operation mode
• Advanced CMOS device requires only a single +5 V
power supply
Applications
• Internal timing system for Channel Banks, Digital
Loop Carriers, Multiplexers, Internal Timing
Generators, PBX, etc.
• Conversion between 2.048 MHz or 4.096 MHz
backplane rates and 1.544 MHz T1 clock rate
• Conversion between North American
International standards (T1/E1 Converter)
and
Frequency Conversion
CLAD
CLKI
CLKO
HFO
LXP600A
LXP602
LXP604
1.544
2.048
1.544
2.048
1.544
4.096
2.048
1.544
2.048
1.544
4.096
1.544
6.144
6.178
8.192
6.176
8.192
6.176
LXP600A, LXP602 and LXP604 Block Diagram
CLKI
Analog
Phase-Locked
Loop
HFO
Feedback
Divider
Frequency
Converter
Output Divider
CLKO
SEL
FSI
Frame Sync
Generator
FSO
Refer to www.level1.com for most current information.
LXP600A, LXP602 and LXP604 Low Jitter Clock Adapters (CLADs)
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXT600 Pin Assignments
n/c
FSO
n/c
HFO
CLKI
n/c
CLKO
n/c
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
n/c
FSI
n/c
SEL
n/c
n/c
GND
FSO
HFO
CLKI
CLKO
1
2
3
4
8
7
6
5
VCC
FSI
SEL
GND
LXP600ANE
LXP602NE
LXP604NE
LXP600ASE
LXP602SE
LXP604SE
Table 1:
Pin Descriptions
Sym
I/O
DO
DO
Description
Pin #
DIP
1
2
SOIC
2
4
FSO
HFO
Frame Sync Output.
8 kHz, active Low, frame synchronization output
pulse. FSO is synchronized to CLKO and to FSI (if FSI is provided).
High Frequency Output.
HFO is used to derive CLKO. HFO can also clock
external devices. HFO is always a multiple of CLKO (CLKO x2, x3, or x4).
Actual frequencies are determined by device, CLKI and CLKO frequencies
and Mode Select (SEL) input, as listed in Table 2.
3
4
5
6
5
7
9
12
CLKI
CLKO
GND
SEL
DI
DO
S
DI
Clock Input.
Input clock (1.544, 2.048 or 4.096 MHz) to be converted.
Clock Output.
Output clock (1.544, 2.048 or 4.096 MHz) derived from
CLKI.
Ground.
Mode Select.
Controls the frequency conversion as listed in Table 2.
When SEL = High, higher frequency CLKI (2.048 for LXP600A and
LXP602, or 4.096 MHz for LXP604) is converted to 1.544 MHz CLKO.
When SEL = Low, 1.544 MHz CLKI is converted to higher frequency CLKO
(2.048 for LXP600A and LXP602, or 4.096 MHz for LXP604).
7
8
–
14
16
1, 3, 6, 8,
10, 11,
13 & 15
FSI
VCC
n/c
DI
S
–
Frame Sync Input.
8 kHz, active Low, frame synchronization input pulse.
Tie this pin High or Low if not used.
Power Supply.
+5 VDC power supply input.
Not Connected.
These pins must be left unconnected.
1. DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output; S = Supply.
2
LXP600A, LXP602 and LXP604 Functional Description
FUNCTIONAL DESCRIPTION
The CLADs convert an input clock (CLKI) at a particular
frequency to an output clock (CLKO) at a different
frequency. They also produce a frame sync output (FSO)
and a high frequency output (HFO) clock. The HFO is a
multiple (2x, 3x, or 4x) of CLKO. The HFO and CLKI/
CLKO conversion frequencies are different for each
device, and controlled by the Mode Select input pin as
specified in Table 2.
The LXP600A and LXP602 convert between 1.544 MHz
and 2.048 MHz. When converting from 2.048 MHz to
1.544 MHz, both CLADs produce a 6.176 MHz HFO.
However, when converting from 1.544 MHz to 2.048
MHz, the LXP600A produces a 6.144 MHz HFO and the
LXP602 produces an 8.192 MHz HFO.
The LXP604 converts between 1.544 MHz and 4.096
MHz. When converting from 4.096 MHz to 1.544 MHz the
LXP604 HFO is 6.176 MHz. When converting from 1.544
MHz to 4.096 MHz, the LXP604 produces an 8.192 MHz
HFO.
In both frequency modes, CLKO is frequency-locked to
CLKI. When FSI is applied, CLKO and CLKI are also
phase-locked with FSO and FSI synchronized. Refer to the
“Test Specifications” for detailed timing.
When FSI is first asserted, the CLKI and CLKO rising
edges will be aligned within a maximum of 500 ms.
If FSI is not provided, pin 7 should be tied High or Low.
CLKO and FSO are still generated with the CLKO
frequency-locked to CLKI.
Output Jitter
2.048 MHz or 4.096 MHz to 1.544 MHz
In this mode of operation, the CLADs meet the output jitter
requirements of AT&T Publication 62411. When there is
no jitter on the input clock (CLKI), the maximum jitter on
CLKO is 0.020 UI pp with no bandlimiting, 0.010 UI pp
over the range of 10 Hz to 40 kHz, and 0.012 UI pp in the
8 - 40 kHz band.
Table 2:
CLAD
LXP600A
LXP602
LXP604
CLAD Frequency Conversions
CLKI
1.544
2.048
1.544
2.048
1.544
4.096
CLKO
2.048
1.544
2.048
1.544
4.096
1.544
HFO
6.144
6.178
8.192
6.176
8.192
6.176
SEL
Low
High
Low
High
Low
High
1.544 MHz to 2.048 MHz or 4.096 MHz
In this mode of operation, the CLADs meet the output jitter
requirements of CCITT Recommendation G.823. When
there is no jitter on the input clock (CLKI), the maximum
jitter on CLKO is 0.035 UI pp over the range of 20 Hz to
100 kHz, and 0.025 UI pp in the 18 - 100 kHz band.
Jitter Transfer
The CLADs are sensitive to jitter on the input clock in
certain frequency bands. The jitter transfer curve is
determined by the frequency and amplitude of the input
jitter. Figures 4 and 5 on page 7 show nominal jitter
transfer measured in nanoseconds. These figures graph
output jitter (less intrinsic jitter) divided by input jitter
(0.25 UI). Jitter transfer from a 2.048 MHz CLKI to a
1.544 MHz CLKO is shown in Figure 4. In this mode, jitter
in the critical 8 kHz band is slightly attenuated while jitter
in the 18 - 70 kHz band is transferred with a small net gain.
Jitter transfer from a 1.544 MHz CLKI to a 2.048 MHz
CLKO is shown in Figure 5. In both modes, with an input
jitter level of 0.25 UI, jitter transfer is held below a net gain
of 1.110.
Note that Jitter transfer varies with input jitter.
Performance in a specific application should be verified in
the actual circuit.Application Information
Mode Select
The Mode Select (SEL) input controls frequency
conversion as follows:
•
2.048 or 4.096 to 1.544 MHz:
To produce a
1.544 MHz output clock from a 2.048 MHz or
4.096 MHz input clock, SEL must be set High. In this
mode HFO = 6.176 MHz for all CLADs.
•
1.544 to 2.048 MHz or 4.096 MHz:
To produce a
2.048 MHz or 4.096 MHz output clock from a 1.544
MHz input clock, SEL must be set Low. In this mode
the LXP600A HFO = 6.144 MHz, and the LXP602
and LXP604 HFO = 8.192 MHz.
3
LXP600A, LXP602 and LXP604 Low Jitter Clock Adapters (CLADs)
APPLICATION INFORMATION
Power-up
Standard CMOS device precautions apply to the CLAD.
Inputs must be applied either simultaneously with or after
the power supply VCC. CLAD input signals include
CLKI, FSI and SEL. The CLAD internal circuitry takes a
maximum of 200 ms to stabilize. There is an additional
delay of 500 ms maximum for CLKO to become phase-
locked to the incoming clock (CLKI) during frame
synchronization FSI.
Figure 2: Typical TP to Coax Adapter Application Circuit
LXP60x
CLAD
GND
FSI
FSO
HFO
CLKI
VCC
SEL
1.544 MHz
CLKO
0.1
µ
F
From FSI Generator Circuit
(See Figure 3)
8 kHz
8 kHz
+5V
LXT304A
TRANSCEIVER
To/From 6.176 MHz
System
Backplane 2.048 or
4.096 MHz
TCLK
TPOS
TNEG
TCLK
TPOS
TNEG
BACKPLANE
T1 / ESF
FRAMER
RNEG
RPOS
RCLK
RNEG
RPOS
RCLK
1.544
MHz
0.1
µ
F
HFO
FSO
From FSI 8 kHz
Generator
Circuit
(See Figure 3)
FSI
VCC
GND
SEL
2.048 or
4.096 MHz
To/From
System
Backplane
6.144 or
8.192 MHz
8 kHz
LXP60x
CLAD
CLKI
CLKO
+5V
4
LXP600A, LXP602 and LXP604 Application Information
Power Supply Decoupling
and Filtering
The CLADs are designed to meet AT&T Publication
62411 specifications for jitter in the range from 10 Hz to
100 kHz. Proper power supply decoupling is critical for
meeting these specifications. As shown in Figure 2, a
typical application with a pair of CLADs for backplane
frequency conversion, a standard 0.1 µF bypass capacitor
is recommended.
The CLADs are monolithic silicon devices which
incorporate both analog and digital circuits. CLAD
application circuit design may require closer attention to
power supply filtering and bypassing than required for pure
digital devices.
Switching power supplies which operate below 100 kHz
may produce noise spikes which can affect the analog
sections of the CLAD. These spikes should be filtered
with an RC network at the CLAD VCC pin.
Frame Sync Generation
A frame sync pulse (FSI) is required to synchronize the
input and output clocks. If a frame sync pulse is not
provided on the backplane, one can be generated from the
existing 2.048 MHz backplane clock. A typical FSI
generation circuit is shown in Figure 3.
Figure 3: Frame Sync (FSI) Generation Circuit
+5V
LS163
Binary Ctr
LS163
Binary Ctr
2.048 MHz
System
Clock
D3
D2
D1
D0
Q3
Q2
Q1
Q0
D3
D2
D1
D0
Q3
Q2
Q1
Q0
LS74
PR
D
Q
System Frame
Sync Output
FSI to CLAD
CLK
T
Ripple
P
Carry
LD CL
CLK
T
Ripple
P
Carry
LD CL
CLK Q
CL
5
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