1 GigaBit Stacked DDR1 SDRAM
DD55E, DD55ER
Features
128M x 8
•
Low Profile 66 Ball Two-High Stacked Die
micropede
™
BGA
•
77% Space Savings Over Two 66 Pin TSOP Packages
•
50% Space Savings Over Two 60 Ball BGA Packages
•
Significant Space Savings and Reduced Parasitics and
•
•
•
•
•
•
•
Trace Lengths Compared to Two BGA Packages
Lead Free - High Temp Solder Balls Available
(DD54ER)
Data Rates Up to 400 Mb per Second
Organization: 4 Banks x 32M x 8 bits
V
DD
= 2.5V ±0.2V, V
DDQ
= 2.5V ±0.2V
V
DD
= 2.6V ±0.1V, V
DDQ
= 2.6V ±0.1V (DDR400)
2.5V I/O (SSTL_2 Compatible)
Bidirectional Data Strobe (DQS) Transmitted/
Received with Data Capture, i.e. Source Synchronous
Data
Differential Clock Inputs, CK AND CK#
10 x 12 x 1.35 mm
micropede
™
BGA
connecting the two 8-bit wide die with all signals in com-
mon except for the Chip Select and the Clock Enable
pins. This scheme dramatically reduces the pin count,
allows versatility, and supports future system upgrades
utilizing the same pin-out.
Double data rate architecture prefetches two words from
the memory array and then transfers the two data
words out on each half clock cycle. Thus, a single read
or write access transfer consists of a double-wide one-
clock cycle data transfer at the internal DRAM core and
two corresponding single-word data transfers at the IO
pins – one on each edge of the clock.
A bidirectional data strobe (DQS) is transmitted exter-
nally, along with the data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller dur-
ing WRITEs.
The DDR SDRAM operates from a differential clock (CK
and CK#) since each edge needs to be precise. Com-
mands (address and control signals) are registered on
the positive going edge of CK.
Read and Write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and con-
•
•
Commands Entered on Each Positive Clock Edge
•
DQS Edge-Aligned with Data for READs, Center-
•
•
•
•
•
•
•
•
•
•
Aligned with Data for WRITEs
DLL to align DQ and DQS Transitions with CK
Programmable Burst Lengths: 2, 4, or 8
8K Refresh
8K Row Addressing (A0—A12)
4 Bank Addressing (BA0, BA1)
2K Column Addressing (A0—A9, A11)
t
RAS
Lockout (t
RAP
= t
RCD
)
Concurrent Auto Precharge Option Supported
Four Internal Banks for Concurrent Operation
Low Thermal Resistance: Theta (JB) = 5.95 °C/W
General Description
The device is a 2.5 volt, 1 gigabit (1,073,741,824 bit)
high speed DDR1 Double Data Rate Synchronous DRAM
organized as 4 banks x 32M x 8 bits in a 66 ball
micropede
™
BGA
.
The high speed throughput is
achieved by minimizing the in-
ternal package interconnect.
The
micropede
™
BGA has less
than half of the inductance of a
standard TSOP package. VCI
stacks two die to create a
mi-
cropede
™
. The
micropede
™,
a
CSP die stack, is mounted on a
BGA substrate allowing two die
to occupy the same board
space as a single monolithic
packaged part.
The high speed data through-
put is also achieved by inter-
VCI reserves the right to change products or specifications without notice.
DD128M82U3BA DD55E published 11/20/06
VCI Proprietary
Ordering Information
Part ID
Solder
Balls
Leaded
Leaded
Leaded
Lead Free
Lead Free
Lead Free
Clock Frequency/Data Rate
133MHz/267Mbps @ CL2.5
167MHz/333Mbps @ CL2.5
200MHz/400Mbps @ CL3
133MHz/267Mbps @ CL2.5
167MHz/333Mbps @ CL2.5
200MHz/400Mbps @ CL3
CL-t
RCD
-t
RP
(t
CK
)
2.5-3-3
2.5-3-3
3-3-3
2.5-3-3
2.5-3-3
3-3-3
DD128M82U3BA7
DD128M82U3BA6
DD128M82U3BA5
DD128M82U3BB7
DD128M82U3BB6
DD128M82U3BB5
*CL = CAS (Read) Latency
Page 1
of 4
engineering@verticalcircuits.com
831.438.3887x132
714.745.4522
Vertical Circuits, Inc.
Embedded System
京公网安备 11010802033920号
EEWORLD
