DPSD8MX16RY5-DP-XX152M datasheet, PDF

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DPSD8MX16RY5-DP-XX152M: DescriptionSynchronous DRAM Module, 8MX16, CMOS, PDMA54, LEADLESS, STACK, TSOP-54; Categorystorage storage; File Size237KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPSD8MX16RY5-DP-XX152M Overview

Synchronous DRAM Module, 8MX16, CMOS, PDMA54, LEADLESS, STACK, TSOP-54

DPSD8MX16RY5-DP-XX152M Parametric

Parameter Name	Attribute value
Parts packaging code	DMA
package instruction	,
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDMA-G54
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
organize	8MX16
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal location	DUAL
Base Number Matches	1

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8Mx16, 7.5 - 15ns, P12, M-Densus

30A220-00

128 Megabit Synchronous DRAM

DPSD8MX16RY5

High Density Memory Device

DESCRIPTION:

The

M-Densus

series is a family of interchangeable memory modules. The 128 Megabit SDRAM is a member of

this family which utilizes the new and innovative space saving TSOP stacking technology. The modules are

constructed with 4 Meg x 16 SDRAMs.

This 64 Megabit based

M-Densus

module, the

DPSD8MX16RY5 has been designed to fit in the same

footprint as the 4 Meg x 16 SDRAM TSOP monolithic and

64 Megabit SDRAM based family of

M-Densus

modules.

This allows the memory board designer to upgrade the

memory in their products without redesigning the

memory board, thus saving time and money.

FEATURES:

•

Configuration Available:

8 Meg x 16 bit (with two Chip Selects)

•

Clock Frequency:

[1]

, 83

[1]

, 100, 125

[2]

, 133

[2]

MHz (max.)

•

PC100 and PC133 Compatable

•

3.3V Supply

•

LVTTL Compatible I/O

•

Four Bank Operation

•

Programmable Burst Type, Burst Length,

and CAS Latency

•

4096 Cycles / 64 ms

•

Auto and Self Refresh

•

Package: TSOP Leadless Stack

NOTES: [1] Available in Military and Industrial Temperature Ranges Only.

[2] Available in Commercial Temperature Range Only.

M-Densus

PIN-OUT DIAGRAM

PIN NAMES

A0 - A11

BA0, BA1

DQ0 - DQ15

CAS

RAS

UDQM,

LDQM

CKE

CLK

CS0-CS1

CCQ

SSQ

N.C./RFU

Row Address:

A0 - A11

Column Address: A0 - A7

Bank Select Address

Data In / Data Out

Column Address Strobes

Row Address Enables

Data Write Enable

Upper & Lower

Data Input/Output Mask

Clock Enable

System Clock

Chip Selects

Power Supply/Ground

Data Output Power/Ground

No Connect

Reserved for Future Use

FUNCTIONAL BLOCK DIAGRAM

30A220-00

REV. B

This document contains information on a product that is currently

released to production at Dense-Pac Microsystems, Inc. Dense-Pac

reserves the right to change products or specifications herein without prior

notice.

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