Memory for Plug & Play
DDR2/DDR3
SPD Memory (for Memory Modules)
BR34E02FVT-3,BR34E02NUX-3
●Description
BR34E02-3 Series is 256×8 bit Electrically Erasable PROM (Based on Serial Presence Detect)
●Features
1) 256×8 bit architecture serial EEPROM
2) Wide operating voltage range: 1.7V-5.5V
3) Two-wire serial interface
4) Self-Timed Erase and Write Cycle
5) Page Write Function (16byte)
6) Write Protect Mode
Settable Reversible Write Protect Function: 00h-7Fh
Write Protect 1 (Onetime Rom)
: 00h-7Fh
Write Protect 2 (Hardwire WP PIN)
: 00h-FFh
7) Low Power consumption
Write
(at 1.7V ) : 0.4mA (typ.)
Read
(at 1.7V ) : 0.1mA(typ.)
Standby ( at 1.7V ) : 0.1µA(typ.)
8) DATA security
Write protect feature (WP pin)
Inhibit to WRITE at low V
CC
9) Compact package: TSSOP-B8, VSON008X2030
10) High reliability fine pattern CMOS technology
11) Rewriting possible up to 1,000,000 times
12) Data retention: 40 years
13) Noise reduction Filtered inputs in SCL / SDA
14) Initial data FFh at all addresses
●BR34E02-3
Series
Capacity
2Kbit
Bit format
256X8
Type
BR34E02-3
Power Source Voltage
1.7V½5.5V
TSSOP-B8
●
VSON008X2030
●
No.11002EAT05
●Absolute
maximum ratings (Ta=25℃)
Parameter
Supply Voltage
Power Dissipation
Storage Temperature
Operating Temperature
Terminal Voltage (A0)
Terminal Voltage (etcetera)
Symbol
V
CC
Pd
Tstg
Topr
-
-
Ratings
-0.3½+6.5
330(BR34E02FVT-3) *1
300(BR34E02NUX-3)*2
-65½+125
-40½+85
-0.3½10.0
-0.3½V
CC
+1.0
Unit
V
mW
℃
℃
V
V
* Reduce by 3.3mW(*1), 3.0 mW(*2)/C over 25C
●Recommended
operating conditions
Parameter
Supply Voltage
Input Voltage
Symbol
V
CC
VIN
Ratings
1.7½5.5
0½V
CC
Unit
V
V
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© 2011 ROHM Co., Ltd. All rights reserved.
1/19
2011.11 - Rev.A
BR34E02FVT-3,BR34E02NUX-3
●Memory
cell characteristics(Ta=25℃, V
CC
=1.7½5.5V)
Limits
Parameter
Min.
Typ.
Write / Erase Cycle *1
Data Retention
*1:Not 100% TESTED
Technical Note
Max.
－
－
Unit
Cycles
Years
1,000,000
40
－
－
*1
●Electrical
characteristics - DC(Unless otherwise specified Ta=-40½+85℃, V
CC
=1.7½5.5V)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
"H" Input Voltage
"L" Input Voltage
"L" Output Voltage 1
"L" Output Voltage 2
Input Leakage Current 1
Input Leakage Current 2
Input Leakage Current 3
Output Leakage Current
VIH
VIL
VOL1
VOL2
ILI1
ILI2
ILI3
ILO
ICC1
Operating Current
ICC2
Standby Current
A0 HV Voltage
ISB
VHV
-
-
7
-
-
-
0.5
2.0
10
mA
µA
V
0.7 V
CC
-0.3
-
-
-1
-1
-1
-1
-
-
-
-
-
-
-
-
-
-
Vcc+1.0
0.3 V
CC
0.4
0.2
1
15
20
1
2.0
V
V
V
V
µA
µA
µA
µA
mA
Test Condition
IOL=2.1mA, 2.5V≦VCC≦5.5V(SDA)
IOL=0.7mA, 1.7V≦VCC＜2.5V(SDA)
VIN=0V½VCC(A0,A1,A2,SCL)
VIN=0V½VCC(WP)
VIN=VHV(A0)
VOUT=0V½VCC
VCC=5.5V,fSCL=400kHz, tWR=5ms
Byte Write
Page Write
Write Protect
VCC =5.5V,fSCL=400kHz
Random Read
Current Read
Sequential Read
VCC =5.5V,SDA,SCL= VCC
A0,A1,A2=GND,WP=GND
VHV-Vcc≧4.8V
○Note:
This IC is not designed to be radiation-resistant.
●Electrical
characteristics - AC(Unless otherwise specified Ta=-40½+85℃, V
CC
=1.7½5.5V
Parameter
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time *1
SDA and SCL Fall Time *1
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width
(SDA and SCL)
WP Hold Time
WP Setup Time
WP High Period
*1:Not 100%
TESTED
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
Limits
Min.
－
0.6
1.2
－
－
0.6
0.6
0
100
0.1
0.1
0.6
1.2
－
－
0
0.1
1.0
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
Max.
400
－
－
0.3
0.3
－
－
－
－
0.9
－
－
－
5
0.1
－
－
－
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
µs
µs
µs
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© 2011 ROHM Co., Ltd. All rights reserved.
2/19
2011.11 - Rev.A
BR34E02FVT-3,BR34E02NUX-3
●Synchronous
Data Timing
Technical Note
t
R
SCL
t
HD
:STA
SDA
(IN)
t
BUF
SDA
(OUT)
t
F
t
HIGH
SCL
t
SU
:DAT t
LOW
t
HD
:DAT
SDA
DATA(1)
D1
D0
ACK
DATA(n)
ACK
t
PD
t
DH
WP
t
WR
STOP BIT
t
SU
：WP
tHD：WP
Fig.1-(a) Synchronous Data Timing
○
SDA data is latched into the chip at the rising edge
○
of SCL clock.
○
Output data toggles at the falling edge of SCL clock.
Fig.1-(d) WP Timing Of The Write Operation
SCL
SCL
t
SU
:STA
SDA
START BIT
STOP BIT
WP
DATA(1)
DATA(n)
D0
ACK
tHIGH : WP
ACK
tWR
t
HD
:STA
t
SU
:STO
SDA
D1
Fig.1-(b) Start/Stop Bit Timing
Fig.1-(e) WP Timing Of The Write Cancel Operation
SCL
SDA
D0
ACK
WRITE DATA(n)
STOP
CONDITION
t
WR
START
CONDITION
○For
WRITE operation, WP must be "Low" from the rising edge of
the clock (which takes in D0 of first byte) until the end of tWR.
(See Fig.1-(d) ) During this period, WRITE operation can be
canceled by setting WP "High".（See Fig.1-(e)）
○When
WP is set to "High" during tWR, WRITE operation is
immediately ceased, making the data unreliable. It must then
be re-written.
Fig.1-(c) Write Cycle Timing
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© 2011 ROHM Co., Ltd. All rights reserved.
3/19
2011.11 - Rev.A
BR34E02FVT-3,BR34E02NUX-3
●Block
diagram
Technical Note
A0 1
8bit
PROTECT_MEMORY_ARRAY
2Kbit_MEMORY_ARRAY
8 V
CC
8bit
A1 2
ADDRESS
DECODER
8bit
SLAVE , WORD
ADDRESS REGISTER
DATA
REGISTER
7 WP
START
STOP
A2 3
CONTOROL LOGIC
ACK
6 SCL
GND 4
HIGH VOLTAGE GEN.
V
CC
LEVEL DETECT
5 SDA
Fig.2 Block Diagram
●Pinout
diagram and description
Pin Name
A0 1
A1 2
A2 3
GND 4
Fig.3 Pin Configuration
BR34E02FVT-3
BR34E02NUX-3
Input/Output
－
－
IN
IN
IN / OUT
IN
Power Supply
Ground 0V
Functions
8 V
CC
7 WP
6 SCL
5 SDA
V
CC
GND
A0,A1,A2
SCL
SDA
WP
Slave Address Set.
Serial Clock Input
Slave and Word Address,
Serial Data Input, Serial Data Output
Write Protect Input
*2
*1
*1 Open drain output requires a pull-up resistor.
*2 WP Pin has a Pull-Down resistor. Please leave unconnected or
connect to GND when not in use.
●Electrical
characteristics curves
The following characteristic data are typ. value.
6
5
4
VIH1,2[V]
VIL1,2[V]
6
5
4
1
0.8
VOL1[V]
SPEC
3
2
1
0
0.6
3
2
Ta=85℃
Ta=-40℃
Ta=25℃
SPEC
0.4
Ta=85℃
0.2
Ta=85℃
Ta=-40℃
Ta=25℃
0
1
2
VCC[V]
3
4
Ta=25℃
1
SPEC
0
0
1
2
VCC[V]
3
4
0
0
1
2
IOL1[mA]
3
Ta=-40℃
4
2
34:I C
Fig.4 "H" Input Voltage VIH
(A0,A1,A2,SCL,SDA,WP)
1
Fig.5 "L" Input Voltage VIL
(A0,A1,A2,SCL,SDA,WP)
1.2
1
Fig.6 "L" Output Voltage VOL1-IOL1
(V
CC
=2.5V)
16
SPEC
SPEC
12
0.8
0.8
ILI1[
μ
A]
VOL2[V]
0.6
0.6
0.4
4
0.2
ILI2[μA]
8
0.4
SPEC
Ta=85℃
Ta=25℃
0.2
Ta=-40℃
0
0
1
2
IOL2[mA]
3
4
0
0
1
2
VCC[V]
Ta=85℃
Ta=25℃
Ta=-40℃
0
3
4
0
1
Ta=85℃
Ta=25℃
Ta=-40℃
2
VCC[V]
3
4
Fig.7 "L" Output Voltage VOL2-IOL2
(V
CC
=1.7V)
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© 2011 ROHM Co., Ltd. All rights reserved.
Fig.8 Input Leakage Current ILI1
(A0,A1,A2,SCL,SDA)
Fig.9 Input Leakage Current ILI2
(WP)
4/19
2011.11 - Rev.A
BR34E02FVT-3,BR34E02NUX-3
Technical Note
3.5
3
2.5
ICC1,2[mA]
2
1.5
1
0.5
0
0
1
2
VCC[V]
Ta=25℃
Ta=85℃
Ta=-40℃
SPEC1
0.6
SPEC
2.5
SPEC
2
0.5
½SCL=400kHz(V
CC
≧2.5V)
fSCL=100kHz(1.7V≦Vcc＜２．５V)
DATA=AA
SPEC2
0.4
ICC3[mA]
0.3
Ta=85℃
ISB[μA]
½ＳＣＬ=100kHz
DATA=AAh
1.5
0.2
0.1
Ta=25℃
1
0.5
Ta=85℃
Ta=25℃
Ta=-40℃
Ta=-40℃
0
0
3
4
0
1
2
VCC[V]
3
4
0
1
2
VCC[V]
3
4
Fig.10 Write Operating Current ICC1,2
(fSCL=100kHz,400kHz)
Fig.11 Read Operating Current ICC3
(fSCL=400kHz)
Fig.12 Standby Current ISB
10000
Ta=85℃
Ta=25℃
Ta=-40℃
5
5
SPEC2
4
4
SPEC2
1000
SPEC1
fSCL[kHz]
tHIGH[μs]
100
SPEC2
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
2
tLOW[μs]
3
3
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
2
10
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
1
0
1
2
VC C [V]
3
4
1
Ta=25℃
Ta=-40℃
Ta=85℃
SPEC1
SPEC1
Ta=85℃
Ta=25℃
Ta=-40℃
1
0
0
1
2
VCC[V]
3
4
0
0
1
2
VCC[V]
3
4
Fig.13 Clock Frequency fSCL
Fig.14 Data Clock High Period tHigh
Fig.15 Data Clock Low Period tLow
5
5
SPEC2
4
SPEC2
50
0
tHD:DAT(HIGH)[μs]
-50
-100
-150
-200
SPEC1,2
4
tHD:STA[μs]
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
Ta=-40℃
Ta=25℃
Ta=85℃
tSU:STA[μs]
3
3
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
2
2
1
SPEC1
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC1
1
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
0
0
1
2
VCC[V]
3
4
0
0
1
2
VCC[V]
3
4
0
1
2
VCC[V]
3
4
Fig.16 Start Condition Hold Time
tHD:STA
Start Condition Setup Time
Fig.
Fig.18 Data Hold Time
tHD:DAT(High)
50
SPEC1,2
300
300
SPEC2
0
tHD:DAT(LOW)[μs]
200
tSU:DAT(HIGH)[ns]
SPEC1
Ta=85℃
Ta=25℃
Ta=-40℃
200
tSU:DAT(LOW)[ns]
100
Ta=85℃
SPEC1:FAST-MODE
-50
SPEC2:STANDARD-MODE
100
-100
Ta=85℃
0
0
Ta=25℃
-150
Ta=25℃
Ta=-40℃
-100
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
-100
-200
Ta=-40℃
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
-200
0
1
2
VCC[V]
3
4
-200
0
1
2
VCC[V]
3
4
0
1
2
VCC[V]
3
4
Fig.19 Data Hold Time
tHD:DAT(LOW)
Fig.20 Input Data Setup Time
tSU:DAT(HIGH)
Fig.21 Input Data Setup Time
tSU:DAT(LOW)
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© 2011 ROHM Co., Ltd. All rights reserved.
5/19
2011.11 - Rev.A
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