Under development
CMOS 8-Bit Microcontroller
TMP86CP24
TMP86CP24F
The TMP86CP24 is the high-speed, high-performance and low power consumption 8-bit microcomputer,
including ROM, RAM, LCD driver, multi-function timer/counter, serial interface (UART, HSIO), a 10-bit
AD converter and two clock generators on chip.
Product No.
TMP86CP24F
ROM
48 K
8 bits
RAM
2K
8 bits
Package
P-LQFP80-1212-0.50A
EEPROM MCU Emulation Chip
TMP86FP24F
TMP86C948XB
Feautures
8-bit single chip microcomputer TLCS-870/C series
Instruction execution time: 0.25 s (at 16 MHz)
122 s (at 32.768 kHz)
132 types and 731 basic instructions
19 interrupt sources (External: 5, Internal: 14)
Input/output ports (54 pins)
(Out of which 16 pins are also used as SEG pins)
16-bit timer counter: 2 ch
Timer, Event counter, Pulse width measurement, External trigger timer,
Window, PPG output modes
8-bit timer counter: 2 ch
Timer, Event counter, PWM output, Programmable divider output, Capture modes
Time base timer
Divider output function
Watchdog timer
Interrupt source/internal reset generate (programmable)
TMP86CP24
P-LQFP80-1212-0.50A
000707EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance / Handling Precautions.
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
86CP24-1
2003-04-15
Under development
Serial interface
UART: 1ch (The function port for UART is also used as SIO function.)
SIO:
2ch
TMP86CP24
ROM corrective function
Four register bank
1 or 2 bytes replace mode
Address replace mode
10-bit successive approximation type AD converter
Analog input: 8 ch
Five key-on wake-up pins
LCD driver/controller
Built-in voltage booster for LCD driver
With display memory (12 bytes)
LCD direct drive capability (max 24 seg
4 com)
1/4, 1/3, 1/2duties or static drive are programmably selectable
Dual clock operation
Single/dual-clock mode
Nine power saving operating modes
STOP mode:
Oscillation stops. Battery/capacitor back-up.
Port output hold/High-impedance.
CPU stops, and peripherals operate using high-frequency clock of
Time-Base-Timer. Release by falling edge of TBTCR TBTCK setting.
CPU stops, and peripherals operate using high-frequency clock.
Release by interruputs.
CPU stops, and peripherals operate using high and low frequency clock.
Release by interruputs.
CPU stops, and peripherals operate using low-frequency clock of
Time-Base-Timer. Release by falling edge of TBTCR TBTCK setting.
CPU stops, and peripherals operate using low-frequency clock.
Release by interrupts.
CPU stops, and peripherals operate using high and low frequency clock.
Release by interrupts.
SLOW 1, 2 mode: Low power consumption operation using low-frequency clock (32.768 kHz)
IDLE 0 mode:
IDLE 1 mode:
IDLE 2 mode:
SLEEP 0 mode:
SLEEP 1 mode:
SLEEP 2 mode:
Wide operating voltage: 1.8 to 3.6V at 8 MHz/32.768 kHz
2.7 to 3.6V at 16 MHz/32.768 kHz
86CP24-2
2003-04-15
Under development
Pin Assignments
(Top View)
P-LQFP80-1212-0.50A
TMP86CP24
V3
V2
V1
C1
C0
WAKE
VSS
XIN
XOUT
TEST
VDD
(XTIN) P21
(XTOUT) P22
(
STOP
/
INT5
) P20
(BOOT) P23
(
INT0
) P00
(INT1) P01
(INT2) P02
(TC2) P03
P04
(RXD/SI1) P05
(TXD/SO1) P06
(
SCK1
) P07
AVDD
VAREF
RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(SO2) P10
(SI2) P11
(
SCK2
) P12
(
PWM5
/
PDO5
/TC5) P13
(INT3/TC3) P14
(TC1) P15
P30
P31
P32
P33
P34
P35
P36
P37
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
P97 (SEG8)
P96 (SEG9)
P95 (SEG10)
P94 (SEG11)
P93 (SEG12)
P92 (SEG13)
P91 (SEG14)
P90 (SEG15)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P47 (SEG16)
P46 (SEG17)
P45 (SEG18)
P44 (SEG19)
P43 (SEG20)
P42 (SEG21)
P41 (SEG22)
P40 (SEG23/STOP4)
P53
P52
P51 (
DVO
)
P50 (
PPG
)
P67 (AIN7/STOP3)
P66 (AIN6/STOP2)
P65 (AIN5/STOP1)
P64 (AIN4/STOP0)
P63 (AIN3)
P62 (AIN2)
P61 (AIN1)
P60 (AIN0)
Note: BOOT function of P23 is included in only TMP86FP24F.
86CP24-3
2003-04-15
Under development
Block Diagram
I/O port (segment output)
Common outputs
COM3 to COM0
Segment outputs
SEG7 to SEG0
P97 (SEG8) P47 (SEG16)
to
to
P90 (SEG15) P40 (SEG23)
TMP86CP24
I/O port
P37 to P30
Power supply
VDD
VSS
LCD driver circuit
C0
C1
V1
V2
V3
RESET
TEST
P9
P4
P3
LCD power
supply
Address/data bus
LCD voltage
booster circuit
TLCS-870/C
CPU
System control circuit
Standby control circuit
(Key-on wake-up)
Timing generator
Data memory
(RAM)
Program memory
(ROM)
Reset input
test pin
Interrupt Controller
Resonator
connecting
pins
Time base timer
XIN
XOUT
High
frequency
Clock
generator
Low
frequency
16-bit
timer/counter
TC1
TC2
8-bit
timer/counter
TC3
TC5
HSIO
UART
SIO2 SIO1
Watchdog timer
Address/data bus
P2
P6
P1
P0
P5
10-bit
AD converter
P23 to P20
AVDD
VAREF
Analog reference
pins
P67 (AIN7) P15 to P10
to
P60 (AIN0)
I/O ports
P07 to P00
P53 to P50
I/O Ports
86CP24-4
2003-04-15
Under development
Pin Functions
Pin Name
P07 (
SCK1
)
P06 (TXD, SO1)
P05 (RXD, SI1)
P04
P03 (TC2)
P02 (INT2)
P01 (INT1)
P00 (
INT0
)
P15 (TC1)
P14 (TC3,INT3)
P13
(
PWM5
,
PDO5
, TC5)
P12 (
SCK2
)
P11 (SI2)
P10 (SO2)
P23
P22 (XTOUT)
P21 (XTIN)
P20 (
INT5
,
STOP
)
TMP86CP24
Input/Output
I/O (I/O)
I/O (Output)
I/O (Input)
I/O
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (I/O)
I/O (I/O)
I/O (Input)
I/O (Output)
I/O
I/O (Output)
I/O (Input)
I/O (Input)
Functions
8-bit input/output port with latch.
When used as a serial interface output
or UART output, respective output latch
(P0DR) should be set to “1”.
When used as an input port, an serial
interface input, UART input, timer
counter input or an external interrupt
input, respective output control
(P0OUTCR) should be cleared to “0”
after setting P0DR to “1”.
6-bit input/output port with latch.
When used as a timer/counter output or
serial interface output, respective output
latch (P1DR) should be set to “1”. When
used as an input port, a timer counter
input, an external interrupt input or serial
interface input, respective output control
(P1OUTCR) should be cleared to “0”
after setting P1DR to “1”.
Serial clock input/output 1
UART data output, Serial data output 1
UART data input, Serial data input 1
Timer counter 2 input
External interrupt 2 input
External interrupt 1 input
External interrupt 0 input
Timer counter 1 input
Timer counter 3 input,
External interrupt 3 input
PWM5 output, PDO5 output,
Timer/counter 5 input
Serial clock input/output 2
Serial data input 2
Serial data output 2
4-bit input/output port with latch.
When used as an input port or an
external interrupt input, respective
output control (P2OUTCR) should be
cleared to “0” after setting output latch
(P2DR) to “1”.
8-bit input/output port with latch (Nch
high current output). When used as an
input port, respective output control
(P3OUTCR) should be cleared to “0”
after setting output latch (P3DR) to “1”.
7-bit input/output port with latch.
When used as an input port, respective
output latch (P4DR) should be set to “1”
after LCD output control (P4LCR) is
cleared to “0”.
1-bit input/output port with latch.
When used as an input port, the output
latch (P4DR) should be set to “1” after
the LCD output control (P4LCR) is
cleared to “0”. When used as a LCD
output, the P4LCR should be set to “1”
after the STOPCR<STOP4EN> should
be cleared to “0”.
When used as a key on wake up input,
the STOPCR<STOP4EN> should be set
to “1”.
4-bit input/output port with latch. When
used as an input port, respective output
control (P5OUTCR) should be cleared
to “0” after setting output latch (P5DR) to
“1”.
When used as a PPG output or divider
output, respective P5DR should be set
to “1”.
Resonator connecting pins (32.768 kHz)
For inputting external clock, XTIN is used and
XTOUT is opened.
External interrupt input 5 or STOP mode
release signal input
P37 to P30
I/O
P47 (SEG16) to
P41 (SEG22)
I/O (Output)
LCD segment output
P40 (SEG23, STOP4)
I/O (I/O)
LCD segment output
STOP mode release input
P53
P52
P51 (
DVO
)
I/O
I/O (Output)
Divider output
P50 (
PPG
)
I/O (Output)
PPG output
86CP24-5
2003-04-15
京公网安备 11010802033920号
EEWORLD
