FIN1019 3.3V LVDS High Speed Differential Driver/Receiver
April 2001
Revised September 2001
FIN1019
3.3V LVDS High Speed Differential Driver/Receiver
General Description
This driver and receiver pair are designed for high speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The driver translates LVTTL signals to
LVDS levels with a typical differential output swing of
350mV and the receiver translates LVDS signals, with a
typical differential input threshold of 100mV, into LVTTL
levels. LVDS technology provides low EMI at ultra low
power dissipation even at high frequencies. This device is
ideal for high speed clock or data transfer.
Features
s
Greater than 400Mbs data rate
s
3.3V power supply operation
s
0.5ns maximum differential pulse skew
s
2.5ns maximum propagation delay
s
Low power dissipation
s
Power-Off protection
s
100mV receiver input sensitivity
s
Fail safe protection open-circuit, shorted and terminated
conditions
s
Meets or exceeds the TIA/EIA-644 LVDS standard
s
Flow-through pinout simplifies PCB layout
s
14-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
FIN1019M
FIN1019MTC
Package Number
M14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Inputs
R
IN+
L
H
X
D
IN
L
H
X
Open
−
Circuit or Z
H
=
HIGH Logic Level
Z
=
High Impedance
Connection Diagram
Outputs
RE
L
L
H
L
DE
H
H
L
H
D
OUT+
L
H
Z
L
R
OUT
L
H
Z
H
D
OUT−
H
L
Z
H
R
IN−
H
L
X
Fail Safe Condition
Pin Descriptions
Pin Name
D
IN
D
OUT+
D
OUT−
DE
R
IN+
R
IN−
R
OUT
RE
V
CC
GND
NC
Description
LVTTL Data Input
Non-inverting LVDS Output
Inverting LVDS Output
Driver Enable (LVTTL, Active HIGH)
Non-Inverting LVDS Input
Inverting LVDS Input
LVTTL Receiver Output
Receiver Enable (LVTTL, Active LOW)
Power Supply
Ground
No Connect
L
=
LOW Logic Level
X
=
Don’t Care
Fail Safe
=
Open, Shorted, Terminated
© 2001 Fairchild Semiconductor Corporation
DS500506
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FIN1019
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
LVTTL DC Input Voltage (D
IN
, DE, RE)
LVDS DC Input Voltage (R
IN+
, R
IN−
)
LVTTL DC Output Voltage (R
OUT
)
LVDS DC Output Voltage (D
OUT+
, D
OUT−
)
LVDS Driver Short Circuit Current (I
OSD
)
LVTTL DC Output Current (I
O
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
−
0.5V to
+
4.6V
−
0.5V to
+
6V
−
0.5V to 4.7V
−
0.5V to
+
6V
−
0.5V to 4.7V
Continuous
16 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Magnitude of Differential Voltage
(|V
ID
|)
Common-Mode Input Voltage (V
IC
)
Operating Temperature (T
A
)
100 mV to V
CC
0.05V to 2.35V
3.0V to 3.6V
0 to V
CC
−
40
°
C to
+
85
°
C
−
65
°
C to
+
150
°
C
150
°
C
≥
6500V
≥
300V
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
(Note 2)
250
R
L
=
100Ω, See Figure 1
1.125
1.25
350
450
25
1.375
25
V
OUT
=
V
CC
or GND, DE
=
0V
V
CC
=
0V, V
OUT
=
0V or 3.6V
V
OUT
=
0V, DE
=
V
CC
V
OD
=
0V, DE
=
V
CC
LVTTL Driver Characteristics
V
OH
Output HIGH Voltage
I
OH
= −100 µA,
RE
=
0V,
See Figure 6 and Table 1
I
OH
= −8
mA, RE
=
0V, V
ID
=
400 mV
V
ID
=
400 mV, V
IC
=
1.2V, see Figure 6
V
OL
Output LOW Voltage
I
OL
=
100
µA,
RE
=
0V, V
ID
= −400
mV
See Figure 6 and Table 1
I
OL
= −8
mA, RE
=
0V, V
ID
= −400
mV
V
ID
= −400
mV, V
IC
=
1.2V, see Figure 6
I
OZ
V
TH
V
TL
I
IN
I
I(OFF)
V
IH
V
IL
I
IN
I
I(OFF)
V
IK
Disabled Output Leakage Current
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Current
Power-OFF Input Current
Input HIGH Voltage
Input LOW Voltage
Input Current
Power-OFF Input Current
Input Clamp Voltage
V
IN
=
0V or V
CC
V
CC
=
0V, V
IN
=
0V or 3.6V
I
IK
= −18
mA
−1.5
V
OUT
=
V
CC
or GND, RE
=
V
CC
See Figure 6 and Table 1
See Figure 6 and Table 1
V
IN
=
0V or V
CC
V
CC
=
0V, V
IN
=
0V or 3.6V
2.0
GND
−100
±20
±20
V
CC
0.8
±20
±20
V
CC
−0.2
V
2.4
±20
±20
−8
±8
Max
Units
LVDS Differential Driver Characteristics
V
OD
∆V
OD
V
OS
∆V
OS
I
OZD
I
OFF
I
OS
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
Disabled Output Leakage Current
Power Off Output Current
Short Circuit Output Current
mV
mV
V
mV
µA
µA
mA
0.2
V
0.5
±20
100
µA
mV
mV
µA
µA
V
V
µA
µA
V
LVDS Receiver Characteristics
LVTTL Driver and Control Signals Characteristics
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2
FIN1019
DC Electrical Characteristics
Device Characteristics
I
CC
Power Supply Current
(Continued)
Driver Enabled, Driver Load: R
L
=
100
Ω
Receiver Disabled, No Receiver Load
Driver Enabled, Driver Load: R
L
=
100
Ω,
Receiver Enabled, (R
IN
+
=
1V and R
IN
−
=
1.4V)
or (R
IN
+
=
1.4V and R
OUT
−
=
1V)
Driver Disabled, Receiver Enabled,
(R
IN
+
=
1V and R
IN
−
=
1.4V) or
(R
IN
+
=
1.4V and R
IN
−
=
1V)
Driver Disabled, Receiver Disabled
12.5
mA
12.5
mA
7.0
7.0
4
6
mA
mA
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
Any LVTTL or LVDS Input
Any LVTTL or LVDS Output
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
(Note 3)
Max
Units
Driver Timing Characteristics
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(PP)
t
ZHD
t
ZLD
t
HZD
t
LZD
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(PP)
t
ZH
t
ZL
t
HZ
t
LZ
Differential Propagation Delay
LOW-to-HIGH
Differential Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Part-to-Part Skew (Note 4)
Differential Output Enable Time from Z to HIGH R
L
=
100Ω, C
L
=
10 pF,
Differential Output Enable Time from Z to LOW See Figure 4 and Figure 5
Differential Output Disable Time from HIGH to Z
Differential Output Disable Time from LOW to Z
Propagation Delay LOW-to-HIGH
Propagation Delay HIGH-to-LOW
Output Rise time (20% to 80%)
Output Fall time (80% to 20%)
Pulse Skew | t
PLH
- t
PHL
|
Part-to-Part Skew (Note 4)
LVTTL Output Enable Time from Z to HIGH
LVTTL Output Enable Time from Z to LOW
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
R
L
=
500
Ω,
C
L
=
10 pF,
See Figure 8
|V
ID
|
=
400 mV, C
L
=
10 pF,
See Figure 6 and Figure 7
0.9
0.9
0.5
0.5
0.5
1.0
5.0
5.0
5.0
5.0
R
L
=
100
Ω,
C
L
=
10 pF,
See Figure 2 and Figure 3
0.5
0.5
0.4
0.4
1.5
1.5
1.0
1.0
0.5
1.0
5.0
5.0
5.0
5.0
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Receiver Timing Characteristics
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
5V.
Note 4:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
3
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FIN1019
Note A:
Input pulses have frequency
=
10 MHz, t
R
or t
F
=
2 ns
Note B:
C
L
includes all probe and fixture capacitances
FIGURE 1. Differential Driver DC Test Circuit
FIGURE 2. Differential Driver Propagation Delay and
Transition Time Test Circuit
Note B:
Input pulses have the frequency
=
10 MHz, t
R
or t
F
=
2 ns
Note A:
C
L
includes all probe and fixture capacitances
FIGURE 3. AC Waveforms for Differential Driver
FIGURE 4. Differential Driver Enable and
Disable Test Circuit
FIGURE 5. Enable and Disable AC Waveforms
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4
FIN1019
Note A:
Input pulses have frequency
=
10 MHz, t
R
or t
F
=
1ns
Note B:
C
L
includes all probe and fixture capacitance
FIGURE 6. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
V
IA
1.25
1.15
2.4
2.3
0.1
0
1.5
0.9
2.4
1.8
0.6
0
V
IB
1.15
1.25
2.3
2.4
0
0.1
0.9
1.5
1.8
2.4
0
0.6
Resulting Differential
Input Voltage (mV)
V
ID
100
−100
100
−100
100
−100
600
−600
600
−600
600
−600
Resulting Common Mode
Input Voltage (V)
V
IC
1.2
1.2
2.35
2.35
0.05
0.05
1.2
1.2
2.1
2.1
0.3
0.3
5
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