EPSA12BBJJ-29.4912M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Aug 27, 2020)
191 SVHC
ITEM DESCRIPTION
Spread Spectrum Quartz Crystal Clock Oscillators LVCMOS (CMOS) 2.5Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount
(SMD) 29.4912MHz ±50ppm Maximum -40°C to +85°C Power Down -1.50% Down Spread
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
Operating Temperature Range
Supply Voltage
Maximum Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Output Control Function
Power Down Input Voltage (Vih and
Vil)
Power Down Output Enable Time
Power Down Output Disable Time
Standby Current
Spread Spectrum
Modulation Frequency
Period Jitter
Start Up Time
Storage Temperature Range
29.4912MHz
±50ppm Maximum (Inclusive of all conditions: Frequency Stability over the Operating Temperature Range, Supply
Voltage Change, Output Load Change, First Year Aging at 25°C, Shock, and Vibration.)
-40°C to +85°C
2.5Vdc ±5%
-0.5Vdc to +3.2Vdc
18mA Maximum
90% of Vdd Minimum (IOH=-8mA)
10% of Vdd Maximum (IOL=+8mA)
3nSec Maximum (Measured at 10% to 90% of Waveform)
50 ±5(%) (Measured at 50% of waveform)
15pF Maximum
CMOS
Power Down (Disabled Output: High Impedance)
70% of Vdd Minimum or No Connection to Enable Output, 30% of Vdd Maximum to Disable Output
3mSec Maximum
100nSec Maximum
10µA Maximum (Unloaded; Pad 1=Ground)
-1.50% Down Spread
30kHz Minimum, 32kHz Typical, 45kHz Maximum
100pSec Maximum (Cycle to Cycle; Spread Spectrum-On)
10mSec Maximum
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 08/29/2012 | Page 1 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EPSA12BBJJ-29.4912M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State or
Power Down
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass
capacitor close (less than 2mm) to the package ground and supply voltage pin is required.
Note 2: A low input capacitance (<12pF), 10X Attentuation Factor, High Impedance (>10Mohms), and
High bandwidth (>300MHz) passive probe is recommended.
Note 3: Capacitance value CL includes sum of all probe and fixture capacitance. See applicable specification sheet
for ‘Load Drive Capability’.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 08/29/2012 | Page 4 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EPSA12BBJJ-29.4912M
Recommended Solder Reflow Methods
High Temperature Infrared/Convection
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
Additional Notes
3°C/Second Maximum
150°C
175°C
200°C
60 - 180 Seconds
3°C/Second Maximum
217°C
60 - 150 Seconds
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
20 - 40 Seconds
6°C/Second Maximum
8 Minutes Maximum
Level 1
Temperatures shown are applied to body of device.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision B 08/29/2012 | Page 5 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
FPGA/CPLD
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