EMD12164P-60 datasheet, PDF - EEWORLD Datasheet

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EMD12164P-60: Description512M: 32M x 16 Mobile DDR SDRAM; File Size898KB，45 Pages; ManufacturerEMLSI; Websitehttp://www.emlsi.com

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512M: 32M x 16 Mobile DDR SDRAM

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Preliminary

EMD12164P

512M: 32M x16 Mobile DDR SDRAM

Document Title

512M: 32M x 16 Mobile DDR SDRAM

Revision History

Revision No.

0.0

Date

Aug 21, 2007

History

Initial Draft

Emerging Memory & Logic Solutions Inc.

4F Korea Construction Financial Cooperation B/D, 301-1 Yeon-Dong, Jeju-Do, Korea Zip Code : 690-717

Tel : +82-64-740-1700 Fax : +82-64-740-1750 / Homepage : www.emlsi.com

The attached datasheets provided by EMLSI reserve the right to change the specifications and products.

EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI

office.

Rev 0.0

Preliminary

EMD12164P

512M: 32M x 16 Mobile DDR SDRAM

Table 2: Pad Description

Symbol

Type

Descriptions

Clock : CK and CKB are differential clock inputs. All address and control input signals are sampled on

the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced

to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived from CK/

CKB.

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operation(all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is

synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.

Input buffers, excluding CK, CKB and CKE, are disabled during power-down and self refresh mode

which are contrived for low standby power consumption.

Chip Select : CSB enables (registered LOW) and disables (registered HIGH) the command decoder. All

commands are masked when CSB is registered HIGH. CSB provides for external bank selection on

systems with multiple banks. CSB is considered part of the command code.

Command Inputs: CASB, RASB, and WEB(along with CSB) define the command being entered.

Input Data Mask : DQM is an input mask signal for write data. Input data is masked when DQM is sam-

pled HIGH along with that input data during a WRITE access. DQM is sampled on both edges of DQS.

Although DQM pins are input-only, the DQM loading matches the DQ and DQS loading. For x16

devices, DQM0 corresponds to the data on DQ0-DQ7, DQM1 corresponds to the data on DQ8-DQ15.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE

command is being applied.

Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO

PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the

respective bank. The address inputs also provide the op-code during a MODE REGISTER SET com-

mand.

Data Bus: Input / Output

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered with

write data. Used to capture write data. For x16 device, DQS0 corresponds to the data on DQ0-DQ7,

DQS1 corresponds to the data on DQ8-DQ15.

CK, CKB

Input

CKE

Input

CSB

RASB, CASB,

WEB

Input

DQM0, DQM1

Input

BA0, BA1

Input

A0 - A12

Input

DQ0-DQ15

DQS0, DQS1

VDD

VSS

VDDQ

VSSQ

I/O

Supply Power Supply

Supply Ground

Supply I/O Power Supply

Supply I/O Ground

Rev 0.0

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Description	512M: 32M x 16 Mobile DDR SDRAM	512M: 32M x 16 Mobile DDR SDRAM	512M: 32M x 16 Mobile DDR SDRAM

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