NVT2001; NVT2002
Bidirectional voltage level translator for open-drain and
push-pull applications
Rev. 3 — 26 April 2012
3
Product data sheet
1. General description
The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V
(V
ref(A)
) and 1.8 V to 5.5 V (V
ref(B)
), which allow bidirectional voltage translations between
1.0 V and 5 V without the need for a direction pin in open-drain or push-pull applications.
Bit widths ranging from 1-bit or 2-bit are offered for level translation application with
transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a
pull-up of 197
.
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (R
on
) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (V
pu(D)
) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by V
ref(B)
. To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.2 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.8 V V
ref(A)
and 3.3 V or 5 V V
ref(B)
2.5 V V
ref(A)
and 5 V V
ref(B)
3.3 V V
ref(A)
and 5 V V
ref(B)
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
Low 3.5
ON-state connection between input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 4 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
3. Ordering information
Table 1.
Ordering information
T
amb
=
40
C to +85
C.
Type number
NVT2001GM
NVT2002DP
[2]
NVT2002GD
[2]
Topside
mark
N1X
[1]
N2002
N02
Number Package
of bits
Name
1
2
2
XSON6
TSSOP8
XSON8U
Description
Version
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3
2
0.5 mm
[1]
[2]
‘X’ will change based on date code.
GTL2002 = NVT2002.
4. Functional diagram
VREFA
VREFB
NVT20xx
EN
A1
SW
B1
An
SW
Bn
GND
002aae132
Fig 1.
Logic diagram of NVT2001; NVT2002 (positive logic)
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 26 April 2012
2 of 22
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
5. Pinning information
5.1 Pinning
5.1.1 1-bit in XSON6 package
NVT2001GM
GND
1
6
EN
VREFA
2
5
VREFB
A1
3
4
B1
002aae211
Transparent top view
Fig 2.
Pin configuration for XSON6
5.1.2 2-bit in TSSOP8 and XSON8U packages
GND
VREFA
GND
VREFA
A1
A2
1
2
3
4
002aae214
1
2
8
7
EN
VREFB
B1
B2
8
7
EN
VREFB
B1
B2
NVT2002GD
A1
A2
3
4
6
5
NVT2002DP
6
5
002aae215
Transparent top view
Fig 3.
Pin configuration for TSSOP8
Fig 4.
Pin configuration for XSON8U
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 26 April 2012
3 of 22
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
5.2 Pin description
Table 2.
Symbol
GND
VREFA
A1
A2
B1
B2
VREFB
EN
[1]
[2]
Pin description
Pin
NVT2001
[1]
1
2
3
-
4
-
5
6
NVT2002
[2]
1
2
3
4
6
5
7
8
ground (0 V)
low-voltage side reference supply voltage for An
low-voltage side; connect to VREFA through a pull-up
resistor
high-voltage side; connect to VREFB through a pull-up
resistor
high-voltage side reference supply voltage for Bn
switch enable input; connect to VREFB and pull-up
through a high resistor
Description
1-bit NVT2001 available in XSON6 package.
2-bit NVT2002 available in TSSOP8 and XSON8U packages.
6. Functional description
Refer to
Figure 1 “Logic diagram of NVT2001; NVT2002 (positive logic)”.
6.1 Function table
Table 3.
Function selection (example)
H = HIGH level; L = LOW level.
Input EN
[1]
H
L
[1]
Function
An = Bn
disconnect
EN is controlled by the V
ref(B)
logic levels and should be at least 1 V higher than V
ref(A)
for best translator
operation.
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 26 April 2012
4 of 22
NXP Semiconductors
NVT2001; NVT2002
Bidirectional voltage level translator
7. Application design-in information
The NVT2001/02 can be used in level translation applications for interfacing devices or
systems operating at different interface voltages with one another. The NVT2001/02 is
ideal for use in applications where an open-drain driver is connected to the data I/Os. The
NVT2001/02 can also be used in applications where a push-pull driver is connected to the
data I/Os.
7.1 Enable and disable
The NVT20xx has an EN input that is used to disable the device by setting EN LOW,
which places all I/Os in the high-impedance state.
V
pu(D)
= 3.3 V
(1)
200 kΩ
V
ref(A)
= 1.8 V
(1)
VREFA
2
NVT2002
8 EN
7
VREFB
RPU
RPU
V
CC
SCL
I
2
C-BUS
MASTER
SDA
GND
RPU
RPU
V
CC
A1
3
SW
6
B1
SCL
I
2
C-BUS
DEVICE
SDA
GND
A2
4
SW
1
GND
5
B2
002aae134
(1) The applied voltages at V
ref(A)
and V
pu(D)
should be such that V
ref(B)
is at least 1 V higher than
V
ref(A)
for best translator operation.
Fig 5.
Typical application circuit (switch always enabled)
Table 4.
Application operating conditions
Refer to
Figure 5.
Symbol
V
ref(B)
V
I(EN)
V
ref(A)
I
sw(pass)
I
ref
T
amb
[1]
Parameter
reference voltage (B)
input voltage on pin EN
reference voltage (A)
pass switch current
reference current
ambient temperature
Conditions
Min
V
ref(A)
+ 0.6
V
ref(A)
+ 0.6
0
-
Typ
[1]
2.1
2.1
1.5
14
5
-
Max
5
5
4.4
-
-
+85
Unit
V
V
V
mA
A
C
transistor
operating in
free-air
-
40
All typical values are at T
amb
= 25
C.
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 26 April 2012
5 of 22