Si514
A
N Y
-F
REQUENCY
I
2
C P
R OG R A MM A B L E
X O ( 1 0 0 k H
Z
Features
TO
250 M H
Z
)
Programmable to any frequency
from 100 kHz to 250 MHz
0.026 ppb frequency tuning
resolution
Glitch suppression on OE, power
on and frequency transitions
1 ps phase jitter (rms, max)
2- to 4-week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO for power supply
noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Industry standard 5 x 7 and
3.2 x 5 mm packages
–40 to 85
o
C operation
Si5602
Ordering Information:
See page 25.
Pin Assignments:
See page 24.
Applications
All-digital PLLs
DAC+ VCXO replacement
SONET/SDH/OTN
3G-SDI/HD-SDI/SDI
Datacom
Industrial automation
FPGA/ASIC clock generation
FPGA synchronization
SDA
SCL
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Description
The Si514 user-programmable I
2
C XO utilizes Silicon Laboratories' advanced PLL
technology to provide any frequency from 100 kHz to 250 MHz with programming
resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and
Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this
range using simple I
2
C commands. Ultra-fine tuning resolution replaces DACs and
VCXOs with an all-digital PLL solution that improves performance where
synchronization is necessary or in free-running reference clock applications. This
solution provides superior supply noise rejection, simplifying low jitter clock
generation in noisy environments. Crystal ESR and DLD are individually
production-tested to guarantee performance and enhance reliability.
The Si514 is factory-configurable for a wide variety of user specifications, including
startup frequency, I
2
C address, supply voltage, output format, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long lead
times and non-recurring engineering charges associated with custom frequency
oscillators.
Functional Block Diagram
Preliminary Rev. 0.9 3/11
Copyright © 2011 by Silicon Laboratories
Si514
Si514
2
Preliminary Rev. 0.9
Si514
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2. Programming a Small Frequency Change (sub ±1000 ppm) . . . . . . . . . . . . . . . . . . 10
2.3. Programming a Large Frequency Change (> ±1000 ppm) . . . . . . . . . . . . . . . . . . . . 11
3. All-Digital PLL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. Register Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1. Dual CMOS (1:2 Fanout Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Si514 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Preliminary Rev. 0.9
3
Si514
1. Electrical Specifications
Table 1. Operating Specifications
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Supply Voltage
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
—
Typ
3.3
2.5
1.8
17
Max
3.63
2.75
1.89
27
Units
V
V
V
mA
Supply Current
I
DD
CMOS, 100 kHz,
single-ended
LVDS
(output enabled)
LVPECL
(output enabled)
HCSL
(output enabled)
Tristate
(output disabled)
—
—
—
—
–40
21
37
32
—
—
26
42
35
18
85
mA
mA
mA
mA
o
Operating Temperature
T
A
C
Table 2. Input Characteristics
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
SDA, SCL Input Voltage High
SDA, SCL Input Voltage Low
Symbol
V
IH
V
IL
Test Condition
Min
0.75 x V
DD
—
Typ
—
—
Max
—
0.25 x V
DD
Units
V
V
4
Preliminary Rev. 0.9
Si514
Table 3. Output Clock Frequency Characteristics
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Programmable
Frequency Range
Frequency
Reprogramming
Resolution
Frequency Range for
Small Frequency Change
(Continuous Glitchless
Output)
Settling time for Small
Frequency Change
Settling time for Large
Frequency Change (Out-
put Squelched during Fre-
quency Transition)
Total Stability
Symbol
F
O
F
O
M
RES
Test Condition
CMOS
LVDS/LVPECL/HCSL
Min
0.100
0.100
—
Typ
—
—
0.026
Max
212.5
250
—
Units
MHz
MHz
ppb
From center frequency
–1000
—
+1000
ppm
<±1000 ppm from
center frequency
>±1000 ppm from
center frequency
—
—
—
—
100
10
µs
ms
Frequency Stability Grade C
1
Frequency Stability Grade B
2
Frequency Stability Grade A
2
–30
–50
–100
–20
–25
–50
—
—
—
—
—
—
—
—
—
—
—
—
+30
+50
+100
+20
+25
+50
10
60
25
ppm
ppm
ppm
ppm
ppm
ppm
ms
µs
µs
Temperature Stability
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Startup Time
Disable Time
T
SU
T
D
Minimum V
DD
until output
frequency (F
O
) within specification
F
O
< 10 MHz
F
O
10 MHz
Notes:
1.
Total stability includes initial accuracy, operating temperature, supply voltage change, load change, and shock and
vibration (not under operation), and 1 year aging at 25
o
C.
2.
Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration
(not under operation), and 10 years aging at 40
o
C.
Preliminary Rev. 0.9
5
FPGA/CPLD
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