SN7476N-00 datasheet, PDF - EEWORLD Datasheet

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SN7476N-00: DescriptionTTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16; Categorylogic logic; File Size516KB，14 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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SN7476N-00 Overview

TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16

SN7476N-00 Parametric

Parameter Name	Attribute value
package instruction	DIP,
Reach Compliance Code	unknown
Other features	MASTER SLAVE OPERATION
series	TTL/H/L
JESD-30 code	R-PDIP-T16
length	19.305 mm
Load capacitance (CL)	15 pF
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Maximum supply current (ICC)	20 mA
propagation delay (tpd)	40 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
width	7.62 mm
minfmax	15 MHz
Base Number Matches	1

SN7476N-00 Related Products

	SN7476N-00	SN5476W-00	SN74LS76ADR	SN5476J-00	SN5476W-10	SN74LS76AN	SN74LS76AD	SN7476N-10	SN7476J	SN7476J-00
Description	TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16	TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16	Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-SOIC 0 to 70	TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16	TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16	Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-PDIP 0 to 70	Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-SOIC 0 to 70	TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16	IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch	IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch
Reach Compliance Code	unknown	unknown	not_compliant	unknown	unknown	not_compliant	not_compliant	unknown	not_compliant	unknown
Other features	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION	MASTER SLAVE OPERATION
series	TTL/H/L	TTL/H/L	LS	TTL/H/L	TTL/H/L	LS	LS	TTL/H/L	TTL/H/L	TTL/H/L
JESD-30 code	R-PDIP-T16	R-GDFP-F16	R-PDSO-G16	R-GDIP-T16	R-GDFP-F16	R-PDIP-T16	R-PDSO-G16	R-PDIP-T16	R-GDIP-T16	R-GDIP-T16
length	19.305 mm	10.2 mm	9.9 mm	19.56 mm	10.2 mm	19.305 mm	9.9 mm	19.305 mm	19.56 mm	19.56 mm
Load capacitance (CL)	15 pF	15 pF	15 pF	15 pF	15 pF	15 pF	15 pF	15 pF	15 pF	15 pF
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP
Number of digits	2	2	2	2	2	2	2	2	2	2
Number of functions	2	2	2	2	2	2	2	2	2	2
Number of terminals	16	16	16	16	16	16	16	16	16	16
Maximum operating temperature	70 °C	125 °C	70 °C	125 °C	125 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED
encapsulated code	DIP	DFP	SOP	DIP	DFP	DIP	SOP	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK	SMALL OUTLINE	IN-LINE	FLATPACK	IN-LINE	SMALL OUTLINE	IN-LINE	IN-LINE	IN-LINE
Maximum supply current (ICC)	20 mA	20 mA	6 mA	20 mA	20 mA	6 mA	6 mA	20 mA	20 mA	20 mA
propagation delay (tpd)	40 ns	40 ns	20 ns	40 ns	40 ns	20 ns	20 ns	40 ns	40 ns	40 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	2.03 mm	1.75 mm	5.08 mm	2.03 mm	5.08 mm	1.75 mm	5.08 mm	5.08 mm	5.08 mm
Maximum supply voltage (Vsup)	5.25 V	5.5 V	5.25 V	5.5 V	5.5 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.5 V	4.75 V	4.5 V	4.5 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	NO	YES	NO	YES	NO	NO	NO
technology	TTL	TTL	TTL	TTL	TTL	TTL	TTL	TTL	TTL	TTL
Temperature level	COMMERCIAL	MILITARY	COMMERCIAL	MILITARY	MILITARY	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	THROUGH-HOLE	FLAT	GULL WING	THROUGH-HOLE	FLAT	THROUGH-HOLE	GULL WING	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE
width	7.62 mm	6.73 mm	3.9 mm	7.62 mm	6.73 mm	7.62 mm	3.9 mm	7.62 mm	7.62 mm	7.62 mm
minfmax	15 MHz	15 MHz	45 MHz	15 MHz	15 MHz	45 MHz	45 MHz	15 MHz	15 MHz	15 MHz
package instruction	DIP,	-	PLASTIC, SOIC-16	-	-	PLASTIC, MS-001BB, DIP-16	PLASTIC, SOIC-16	DIP,	DIP, DIP16,.3	-
Base Number Matches	1	1	1	1	1	1	1	1	1	-
Maker	-	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	-	Texas Instruments	Texas Instruments

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