Product Specification
PE4230
Product Description
The PE4230 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from DC through 3000 MHz. This
single-supply reflective switch integrates on-board CMOS
control logic driven by a simple, single-pin CMOS or TTL
compatible control input. Using a nominal +3-volt power supply,
a typical input 1 dB compression point of +32 dBm can be
achieved. The PE4230 also exhibits input-output isolation of
better than 39 dB at 1000 MHz and is offered in a small 8-lead
MSOP package.
The PE4230 SPDT High Power UltraCMOS™ RF Switch is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering the performance of GaAs with
the economy and integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
SPDT High Power UltraCMOS™
RF Switch
Features
•
Single 3-volt power supply
•
Low insertion loss: 0.35 dB at
1000 MHz, 0.55 dB at 2000 MHz
•
High isolation of 39 dB at 1000 MHz,
30 dB at 2000 MHz
•
Typical input 1 dB compression point
of +32 dBm
•
Single-pin CMOS or TTL logic control
•
Low cost
RF1
RF2
CMOS
Control
Driver
CTRL
Parameter
Operation Frequency
1
Insertion Loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Video Feedthrough
2
Input 1 dB Compression
Input IP3
O
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(Z
S
= Z
L
= 50
Ω
)
Conditions
Minimum
DC
0.35
38
28
33.5
26.5
23.5
14.5
0.55
39
30
35
28
25.5
15.4
200
90
15
2000 MHz
2000 MHz, 17 dBm
30
50
32
bs
o
le
Typical
Maximum
3000
0.45
0.65
te
Figure 2. Package Type
8-lead MSOP
Units
MHz
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
mV
pp
dBm
dBm
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
CTRL to 0.1 dB final value, 2 GHz
CTRL to 25 dB isolation, 2 GHz
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50
Ω
test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Document No. 70-0029-02
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4230
Product Specification
Figure 3. Pin Configuration (Top View)
V
DD
CTRL
GND
1
2
8
7
RF1
GND
GND
RF2
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any input
except for the CTRL input
Voltage on CTRL input
Storage temperature range
Operating temperature
range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
Max
4.0
V
DD
+
0.3
5.0
150
85
35
250
Units
V
V
V
°C
°C
dBm
V
4230
3
4
6
5
V
CTRL
T
ST
T
OP
-65
-40
RFC
P
IN
V
ESD
Table 2. Pin Descriptions
Pin
No.
1
2
Pin
Name
V
DD
CTRL
Description
Nominal +3V supply connection.
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Common RF port for switch.
1
RF2 port.
1
le
3
GND
Table 5. Control Logic Truth Table
Control Voltage
Signal Path
RFC to RF1
RFC to RF2
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
4
5
6
RFC
RF2
GND
7
GND
8
RF1
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
Table 3. DC Electrical Specifications
Parameter
V
DD
Power Supply Voltage
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
Control Voltage High
Control Voltage Low
0.7xV
DD
0.3xV
DD
O
Typ
3.0
29
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
RF1 port.
1
Min
2.7
bs
o
Max
3.3
35
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic driv-
ers, the control logic input has been designed to
handle a 5-volt logic HIGH signal. (A minimal cur-
rent will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
Latch-Up Avoidance
Units
V
µA
V
V
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
©2005 Peregrine Semiconductor Corp. All rights reserved.
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te
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Document No. 70-0029-02
│
UltraCMOS™ RFIC Solutions
PE4230
Product Specification
Typical Performance Data @ 25 °C (Unless Otherwise Noted)
Figure 4. Insertion Loss – RFC to RF1
T = -40 °C to 85 °C
0
-40
8C
-0.4
85
8C
-0.8
Figure 5. Input 1dB Compression Point
40
1dB Compression Point (dBm)
25
8C
Insertion Loss (dB)
30
20
-1.2
-1.6
0
500
1000
1500
2000
2500
3000
le
0
-20
Isolation (dB)
-40
-60
-80
-100
0
-2
te
10
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
500
1000
1500
2000
2500
3000
Frequency (MHz)
Frequency (MHz)
Figure 6. Insertion Loss – RFC to RF2
T = -40 °C to 85 °C
0
-0.4
25
8
C
Insertion Loss (dB)
85
8
C
-0.8
-1.2
-1.6
-2
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
Document No. 70-0029-02
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O
-40
8
C
bs
o
Figure 7. Isolation – RFC to RF1
©2005 Peregrine Semiconductor Corp. All rights reserved.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4230
Product Specification
Typical Performance Data @ 25°C
Figure 8. Isolation – RFC to RF2
Figure 9. Isolation – RF1 to RF2, RF2 to RF1
0
0
-20
-20
RF2
Isolation (dB)
Isolation (dB)
-40
-40
RF1
-60
-60
-80
0
500
1000
1500
2000
2500
le
0
0
-10
Return Loss (dB)
-20
-30
-40
0
-100
te
-80
-100
500
1000
1500
2000
2500
3000
Frequency (MHz)
Frequency (MHz)
Figure 10. Return Loss – RFC
0
-10
Return Loss (dB)
O
bs
o
2500
3000
Figure 11. Return Loss – RF1, RF2
RF2
-20
RF1
-30
-40
0
500
1000
1500
2000
500
1000
1500
2000
2500
Frequency (MHz)
Frequency (MHz)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 7
Document No. 70-0029-02
│
UltraCMOS™ RFIC Solutions
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4230
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4230 SPDT switch. The RF common port is
connected through a 50
Ω
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
Ω
transmission lines to the
top two SMA connectors on the right side of the
board, J3 and J4. A through transmission line
connects SMA connectors J6 and J8. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.030”, trace
gaps of 0.007”, dielectric thickness of 0.028”,
metal thickness of 0.0014” and
ε
r
of 4.4.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J2-3) is connected
to the device CNTL input. The fourth pin to the
right (J2-7) is connected to the device V
DD
input.
A decoupling capacitor (100 pF) is provided on
both CNTL and V
DD
traces. It is the responsibility
of the customer to determine proper supply
decoupling for their design application. Removing
these components from the evaluation board has
not been shown to degrade RF performance.
Figure 12. Evaluation Board Layouts
Peregrine Specification 101/0037
O
Document No. 70-0029-02
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bs
o
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0035
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 7
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
le
te
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