KM29W8000T, KM29W8000IT
Document Title
1M x 8 bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No.
0.0
1.0
History
Data Sheet 1997
Data Sheet 1998
1. Changed t
BERS
parameter : 5ms(Typ.)
→
2ms(Typ.)
10ms(Max.)
→
4ms(Max.)
2. Changed t
PROG
parameter : 1.5ms(Max.)
→
1.0ms(Max.)
Data sheet 1998
1. Cjanged DC and Operating Characteristics
Parameter
Burst Read
Operating
Current Program
Eraase
Stand-by Current (CMOS)
Input Leakage Current
Output Leakage Current
Vcc=2.7V~3.6V
Typ
10
→
5
10
→
5
10
→
5
5
→
10
-
-
Max
20
→
10
20
→
10
20
→
10
50
10
→ ±10
10
→ ±10
Vcc=3.6V~5.5V
Typ
15
→
10
15
→
10
15
→
10
10
-
-
Max
30
→
20
30
→
20
30
→
20
100
→
50
10
→ ±10
10
→ ±10
µA
mA
Unit
Draft Date
April 10th 1997
April 10th 1998
Remark
Advance
Preliminary
1.1
July 14th 1998
Final
1.2
Data Sheet 1999
1) Added CE don’ care mode during the data-loading and reading
t
April 10th 1999
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
KM29W8000T, KM29W8000IT
1M x 8 Bit NAND Flash Memory
FEATURES
•
Voltage supply : 2.7V ~ 5.5V
•
Organization
- Memory Cell Array : (1M + 32K)bit x 8bit
- Data Register
: (256 + 8)bit x8bit
•
Automatic Program and Erase(Typical)
- Page Program : (256 + 8)Byte in 250µs
- Block Erase : (4K + 128)Byte in 2ms
- Status Register
•
264-Byte Page Read Operation
- Random Access
: 10µs(Max.)
- Serial Page Access : 80ns(Min.)
•
System Performance Enhancement
- Ready/ Busy Status Output
•
Command/Address/Data Multiplexed I/O port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
•
Command Register Operation
•
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
FLASH MEMORY
GENERAL DESCRIPTION
The KM29W8000 is a 1M(1,048,576)x8bit NAND Flash Mem-
ory with a spare 32K(32,768)x8bit. Its NAND cell provides the
most cost-effective solution for the solid state mass storage
market. A program operation programs the 264-byte page in
typically 250µs and an erase operation can be performed in
typically 2ms on a 4K-byte block.
Data in the page can be read out at 80ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out-
put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verify and margin-
ing of data. Even the write-intensive systems can take advan-
tage of the KM29W8000 extended reliability of 1,000,000
program/erase cycles by providing either ECC(Error Correction
Code) or real time mapping-out algorithm. These algorithms
have been implemented in many mass storage applications
and also the spare 8bytes of a page combined with the other
256 bytes can be utilized by system-level ECC.
The KM29W8000 is an optimum solution for large nonvolatile
storage application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name
I/O
0
~I/O
7
CLE
ALE
CE
RE
WE
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCC
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
RE
R/B
GND
N.C
N.C
N.C
N.C
N.C
Pin Function
Data Inputs/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ground Input
Ready/Busy output
Power(2.7V ~ 5.5V)
Ground
No Connection
WP
GND
R/B
V
CC
V
SS
N.C
44(40) TSOP (II)
STANDARD TYPE
NOTE
: Connect all V
CC
and V
SS
pins of each device to power supply outputs.
Do NOT leave V
CC
or V
SS
disconnected.
2
KM29W8000T, KM29W8000IT
Figure 1. FUNCTIONAL BLOCK DIAGRAM
v
CC
v
SS
A
8
- A
19
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
8M + 256K Bit
NAND Flash
ARRAY
(256 + 8)Byte x 4096
Page Register & S/A
Y-Gating
Command
Command
Register
FLASH MEMORY
A
0
- A
7
I/O Buffers & Latches
v
CC
v
SS
Output
Driver
I/0
0
I/0
7
CE
RE
WE
Control Logic
& High Voltage
Generator
Global Buffers
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block(=16 Row)
(4K + 128)Byte
8M : 4K Row
(=256 Block)
8 bit
256B Column
8B Column
1 Page = 264 Byte
1 Block = 264 B x 16 Pages
= (4K + 128) Bytes
1 Device = 264B x 16Pages x 256 Blocks
= 8.6 Mbits
Page Register
256 Byte
8 Byte
I/O
0
~ I/O
7
I/O
0
1st Cycle
2nd Cycle
3rd Cycle
A
0
A
8
A
16
I/O
1
A
1
A
9
A
17
I/O
2
A
2
A
10
A
18
I/O
3
A
3
A
11
A
19
I/O
4
A
4
A
12
*X
I/O
5
A
5
A
13
*X
I/O
6
A
6
A
14
*X
I/O
7
A
7
A
15
*X
Column Address
Row Address
(Page Address)
NOTE
: A
12
to A
19
: Block Address
* : X can be V
IL
or V
IH
.
3
KM29W8000T, KM29W8000IT
PRODUCT INTRODUCTION
FLASH MEMORY
The KM29W8000 is an 8.6Mbit(8,650,752 bit) memory organized as 4096 rows by 264 columns. Spare eight columns are located
from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages
formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 256 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29W8000.
The KM29W8000 has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29W8000.
Table 1. COMMAND SETS
Function
Sequential Data Input
Read 1
Read 2
Read ID
Reset
Page Program
Block Erase
Read Status
1st. Cycle
80h
00h
50h
90h
FFh
10h
60h
70h
2nd. Cycle
-
-
-
-
-
-
D0h
-
O
O
Acceptable Command during Busy
4
KM29W8000T, KM29W8000IT
PIN DESCRIPTION
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the devices is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
REA
after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O
0
~ I/O
7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or when outputs are disabled.
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