8xC251TA, 8xC251TB,
8xC251TP, 8xC251TQ,
Hardware Description
Addendum to the 8xC251SA, 8xC251SB,
8xC251SP, 8xC251SQ, User’s Manual
Release Date: November, 1997
Order Number: 273138-001
The 8xC251Tx may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Such errata are not covered by
Intel’s warranty. Current characterized errata are available on request.
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s
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property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel
may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The 8xC251Tx may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
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or call 1-800-548-4725.
Many documents are available for download from Intel’s website at http://www.intel.com.
Copyright © Intel Corporation 1997.
*Third party brands and names are the property of their respective owners.
8xC251Tx Hardware Description
8xC251TA, 8xC251TB, 8xC251TP, 8xC251TQ, Hardware Description
Addendum to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ, User’s Manual
1.0 INTRODUCTION TO THE 8xC251Tx
1.1
Comparing the 8xC251Tx and 8xC251Sx ..................................................................... 1
2.0 SIGNAL SUMMARY
3.0 THE SECOND SERIAL I/O PORT
3.1
Overview........................................................................................................................ 7
3.2
Special Function Register Definitions ............................................................................ 9
3.2.1
SCON1 .................................................................................................................... 9
3.2.2
SBUF1 ................................................................................................................... 10
3.2.3
SADDR1 ................................................................................................................ 10
3.2.4
SADEN1 ................................................................................................................ 10
3.2.5
BGCON .................................................................................................................. 10
3.2.6
IE1 ......................................................................................................................... 11
3.2.7
IPH1 ....................................................................................................................... 11
3.2.8
IPL1 ....................................................................................................................... 11
4.0 EXTENDED DATA FLOAT TIMING
4.1
Summary of the Extended Data Float Timing Changes .............................................. 12
FIGURES
Figure 1
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
8xC251Tx Signal Summary ................................................................................. 2
8xC251Tx Signal Descriptions ............................................................................. 3
Special Function Register (SFR) Map.................................................................. 6
Second Serial I/O Port Signals ............................................................................ 7
Second Serial I/O Port Special Function Registers.............................................. 8
SCON1 Special Function Register Definitions ..................................................... 9
BGCON Special Function Register Definitions .................................................. 10
IE1 Special Function Register Definitions .......................................................... 11
IPH1 Special Function Register Definitions ....................................................... 11
IPL1 Special Function Register Definitions ........................................................ 11
Interrupt Priority of Second Serial I/O Port......................................................... 11
UCONFIG1 bit definitions for the 8xC251Tx ...................................................... 12
Summary of the EDF# and WSB#[1:0] Configuration Options........................... 13
8xC251Tx Block Diagram ..................................................................................... 1
III
8xC251Tx Hardware Description
1.0 INTRODUCTION TO THE 8xC251Tx
This Hardware Description describes the 8xC251TA, 8xC251TB, 8xC251TP, 8xC251TQ (referred to collec-
tively as the 8xC251Tx) embedded microcontroller, which is the newest member of the MCS
®
251 microcon-
troller family. The 8xC251Tx is pin and code compatible with the 8xC251Sx but is enhanced with the addition
of new features.
This document addresses the differences between the two members of the MCS 251 microcontroller family.
For a detailed description of the MCS 251 microcontroller core and standard peripherals shared by both the
8xC251Sx and 8xC251Tx, please refer to the
8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded
Microcontroller User’s Manual
(272795).
1.1
Comparing the 8xC251Tx and 8xC251Sx
The differences between the 8xC251Tx and the 8xC251Sx are briefly described here.
•
•
•
The maximum operating frequency of the 8xC251Tx is 24 Mhz compared to 16 MHz for the 8xC251Sx.
The 8xC251Tx has two serial I/O ports while the 8xC251Sx has one. The pins for the second serial I/O
port are multiplexed with other functional pins.
The 8xC251Tx has a new configuration option (Extended Data Float timing) to allow interfacing with
slower memories. This feature is supported by a bit in the configuration byte, UCONFIG1. The corre-
sponding bit in the 8xC251Sx has a different function.
The 8xC251Tx is offered in with factory programmed ROM while the 8xC251Sx is also offered with
OTPROM/EPROM.
•
P0 (A7-
0/D7-0)
RESET
Clock and
Reset Unit
P2 (A15-8)
PORT
0-3
EPROM/
ROM
RAM
XTAL2
Interrupt
Handler Unit
8
16
Memory Data
Data Bus
24
Data Address
Peripheral Interface Unit
Memory Address
16
IB Bus
Peripherals
P3
BUS INTERFACE UNIT
8
3 Timers
XTAL1
16
INSTR
Instruction
Sequencer
24
PC
CPU
Data Memory Interface
Serial I/O
WDT
SRC1, SRC2
PSEN
ALU
Register
File
DST
ALE
Program
Counter
PCA
P1
2nd Serial
I/O
VCC
VSS
Figure 1. 8xC251Tx Block Diagram
1
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