Features
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Incorporates the ARM7TDMI
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ARM
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Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
8K Bytes On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
1M Words 16-bit Flash Memory (16 Mbits)
– Single Voltage Read/Write, 110 ns Access Time
– Sector Erase Architecture
– Fast Word Program Time of 20 µs; Fast Sector Erase Time of 200 ms
– Dual-plane Organization Allows Concurrent Read and Program/Erase
– Erase Suspend Capability
– Low-power Operation: 25 mA Active - 10 µA Standby
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– Factory-programmed AT91 Flash Uploader Software
Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– 8 Chip Selects, Software-programmable 8/16-bit External Data Bus
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
32 Programmable I/O Lines
3-channel 16-bit Timer/Counter
– 3 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Programmable Watchdog Timer
Advanced Power-saving Features
– CPU and Peripherals Can Be Deactivated Individually
Fully Static Operation:
– 0 Hz to 40 MHz Internal Frequency Range at 3.0V, 85°C
2.7V to 3.6V Operating Range
-40°C to 85°C Temperature Range
Available in a 120-ball BGA Package
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AT91 ARM
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Microcontrollers
AT91F40816
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Description
The AT91F40816 is a member of the Atmel AT91 16/32-bit microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption. In addition, a large number of internally banked registers result in
very fast exception handling, making the device ideal for real-time control applications.
The eight-level priority-vectored interrupt controller, together with the Peripheral Data
Controller, significantly enhance real-time device performance.
By combining the microcontroller, featuring on-chip SRAM and a wide range of periph-
eral functions, with 16 Mbits of Flash memory in a single compact 120-ball BGA
package, the Atmel AT91F40816 provides a powerful, flexible and cost-effective solu-
tion to many compute-intensive embedded control applications and offers significant
board size reductions.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-pro-
grammed Flash Uploader using a single device supply, making the AT91F40816 ideal
for in-system programmable applications.
Rev. 1384C–ATARM–02/02
1
AT91F40816
Pin Description
Table 1.
AT91F40816 Pin Description
Module
Name
A0 - A23
D0 - D15
NCS0 - NCS3
CS4 - CS7
NWR0
NWR1
EBI
NRD
NWE
NOE
NUB
NLB
NWAIT
BMS
Boot Mode Select
FIQ
AIC
IRQ0 - IRQ2
TCLK0 - TCLK2
Timer
TIOA0 - TIOA2
TIOB0 - TIOB2
SCK0 - SCK1
USART
TXD0 - TXD1
RXD0 - RXD1
PIO
WD
Clock
MCKO
NRST
Reset
NTRI
TMS
TDI
ICE
TDO
TCK
Test Data Output
Test Clock
Output
Input
–
–
Schmidt trigger, internal pull-up
Tri-state Mode Select
Test Mode Select
Test Data Input
Input
Input
Input
Low
–
–
Sampled during reset
Schmidt trigger, internal pull-up
Schmidt trigger, internal pull-up
Master Clock Output
Hardware Reset Input
Output
Input
–
Low
Schmidt trigger
P0 - P31
NWDOVF
MCKI
External Interrupt Request
Timer External Clock
Multi-purpose Timer I/O Pin A
Multi-purpose Timer I/O Pin B
External Serial Clock
Transmit Data Output
Receive Data Input
Parallel IO Line
Watchdog Overflow
Master Clock Input
Input
Input
I/O
I/O
I/O
Output
Input
I/O
Output
Input
–
–
–
–
–
–
–
–
Low
–
Open drain
Schmidt trigger
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Fast Interrupt Request
Input
–
Function
Address Bus
Data Bus
External Chip Select
External Chip Select
Lower Byte 0 Write Signal
Upper Byte 1 Write Signal
Read Signal
Write Enable
Output Enable
Upper Byte Select
Lower Byte Select
Wait Input
Type
Output
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Active
Level
–
–
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
–
Sampled during reset; must be driven low
during reset for Flash to be used as boot
memory
PIO-controlled after reset
Used to select external devices
A23 - A20 after reset
Used in Byte Write option
Used in Byte Write option
Used in Byte Write option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Comments
Valid after reset; do not reprogram A20 to
I/O, as it is MSB of Flash address
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1384C–ATARM–02/02
RF/Wirelessly
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